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Analog Circuit with Labview

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Analog Electronics with LabVIEW®
By Kenneth L. Ashley
...............................................
Publisher: Prentice Hall
Pub Date: October 04, 2002
Print ISBN-10: 0-13-047065-1
Print ISBN-13: 978-0-13-047065-2
Pages: 432
Table of Contents | Examples

Copyright
National Improvements | Virtual Instrumentation Series
Preface
References
Hardware and Software Requirements
LabVIEW VI Libraries and Project and Problem Folders and Files
Unit 1. Elementary Circuit Analysis for Analog Electronics
Section 1.1. Resistor Voltage Divider and MOSFET DC Gate Voltage
Section 1.2. Output Circuit and DC Drain Voltage
Section 1.3. Frequency Response of the Amplifier Stage
Section 1.4. Summary of Equations
Section 1.5. Exercises and Projects
Unit 2. Transistors and Voltage Amplification
Section 2.1. BJT and MOSFET Schematic Symbols, Terminal Voltages, and
Branch Currents
Section 2.2. Fundamentals of Signal Amplification: The Linear Circuit
Section 2.3. Basic NMOS Common-Source Amplifier
Section 2.4. Transistor Output Resistance and Limiting Gain
Section 2.5. Summary of Equations
Section 2.6. Exercises and Projects
Section 2.7. References to the Electronics Book Sequence
Unit 3. Characterization of MOS Transistors for Circuit Simulation
Section 3.1. Physical Description of the MOSFET
Section 3.2. Output and Transfer Characteristics of the MOSFET
Section 3.3. Body Effect and Threshold Voltage
Section 3.4. Derivation of the Linear-Region Current – Voltage Relation
Section 3.5. Summary of Equations
Section 3.6. Exercises and Projects
Unit 4. Signal Conductance Parameters for Circuit Simulation
Section 4.1. Amplifier Circuit and Signal Equivalent Circuits
Section 4.2. Transistor Variable Incremental Relationships
Section 4.3. Transconductance Parameter
Section 4.4. Body-Effect Transconductance Parameter
Section 4.5. Output Conductance Parameter

Section 4.6. Graphical Perspective of Output Characteristics and the Load Line
Section 4.7. Summary of Equations
Unit 5. Common-Source Amplifier Stage
Section 5.1. DC (Bias) Circuit
Section 5.2. Amplifier Voltage Gain
Section 5.3. Linearity of the Gain of the Common-Source Amplifier
Section 5.4. Current-Source Common-Source Amplifier: Common-Source
Amplifier with a Source Resistor
Section 5.5. Design of a Basic Common-Source Amplifier
Section 5.6. Summary of Equations
Section 5.7. Exercises and Projects
Unit 6. Coupling and Bypass Capacitors and Frequency Response
Section 6.1. Grounded-Source Amplifier: Coupling Capacitor
Section 6.2. Current-Source Bias Amplifier: Bypass Capacitor
Section 6.3. Precision Formulation of the Low-Frequency Gain and
Characteristic Frequencies
Section 6.4. Load Coupling Capacitor
Section 6.5. Summary of Equations
Section 6.6. Exercises and Projects
Unit 7. MOSFET Source-Follower Buffer Stage
Section 7.1. DC (Bias) Circuit
Section 7.2. Source-Follower Voltage Transfer Relation
Section 7.3. Body Effect and Source-Follower Voltage Transfer Relation
Section 7.4. Summary of Equations
Section 7.5. Exercises and Projects
Unit 8. MOSFET Differential Amplifier Stage
Section 8.1. DC (Bias) Circuit
Section 8.2. DC Imbalances
Section 8.3. Signal Voltage Gain of the Ideal Differential Amplifier Stage
Section 8.4. Effect of the Bias Resistor on Voltage Gain
Section 8.5. Differential Voltage Gain
Section 8.6. Common-Mode Voltage Gain
Section 8.7. Voltage Gains Including Transistor Output Resistance
Section 8.8. Body Effect and Voltage Gain
Section 8.9. Amplifier Gain with Differential and Common-Mode Inputs
Section 8.10. Comparison of Numerical Gain Results
Section 8.11. Summary of Equations
Section 8.12. Exercises and Projects
Unit 9. MOSFET Current Sources
Section 9.1. Basic Current Source
Section 9.2. Current Source with Source Degeneration
Section 9.3. Differential Amplifier Balancing Circuit
Section 9.4. Summary of Equations
Unit 10. Common-Source Amplifier with Current-Source Load
Section 10.1. DC (Bias) Circuit
Section 10.2. Signal Voltage Gain

Section 10.3. Summary of Equations
Section 10.4. Exercises and Projects
Unit 11. Operational Amplifiers with Resistor Negative Feedback
Section 11.1. Operational Amplifiers with Resistance Feedback
Section 11.2. Output Resistance of the Resistor Feedback Amplifier
Section 11.3. Operational Amplifier Offset
Section 11.4. DC Stabilization with the Feedback Resistor
Section 11.5. Frequency Response of the Operational Amplifier and Resistor
Feedback Amplifier
Section 11.6. Summary of Equations
Section 11.7. Exercises and Projects
Unit 12. Operational Amplifier Applications with Capacitors
Section 12.1. Operational Amplifier Integrator
Section 12.2. Operational Amplifier Oscillator
Section 12.3. Summary of Equations
Section 12.4. Exercises and Projects
Unit 13. Cascaded Amplifier Stages
Section 13.1. Combining NMOS and PMOS Circuits in Cascade
Section 13.2. Amplifier Gain of Differential Amplifier and Common-Source
Stage in Cascade
Section 13.3. Stabilization of Signal Gain and Bias Current with a Source
Resistor
Section 13.4. Common-Source Stage as a Series – Series Feedback Circuit
Section 13.5. Shunt – Series Cascade Amplifier
Section 13.6. Summary of Equations
Unit 14. Development of a Basic CMOS Operational Amplifier
Section 14.1. Current-Source Bias for the Differential Amplifier Stage
Section 14.2. Current-Source Output Resistance and Common-Mode Gain
Section 14.3. Current-Source Load for the Common-Source Stage
Section 14.4. Current-Source Load for the Differential Stage
Section 14.5. Two-Stage Amplifier with Current-Source Biasing
Section 14.6. Output Buffer Stage
Section 14.7. Output Resistance of the Feedback Amplifier and Effect on Gain from Loading
Section 14.8. Output Circuit of the TS271 Opamp
Section 14.9. Summary of Equations
Unit A. Communicating with the Circuit Board: LabVIEW Programming and
Measurement Exercises
Section A.1. Basics of Sending and Receiving Circuit Voltages
Section A.2. ADC and the Autoranging Voltmeter
Section A.3. LabVIEW Oscilloscope and Voltmeter (ac)
Section A.4. Measuring the Discrete Characteristics of Sending and Receiving
Voltages
Section A.5. Sending and Receiving Waveforms
Section A.6. Summary of Programming Projects
Unit B. Characterization of the Bipolar Junction Transistor for Circuit Simulation

Section B.1. Fundamentals of Bipolar Junction Transistor Action
Section B.2. Base-Width Dependence on Junction Voltage
Section B.3. BJT Base, Emitter, and Collector Currents in the Active Mode
Section B.4. Diode-Connected Transistor Circuits for Measuring Base and
Collector Current
Section B.5. Output Characteristics of BJT in the Common-Emitter Mode
Section B.6. SPICE Solution for IC versus VCE of the Measurement Circuit
Section B.7. Collector-Emitter Voltage and Collector Current in the Saturation
Region
Section B.8. SPICE BJT βDC as a Function of Collector Current
Section B.9. Signal or Incremental Common-Emitter Current Gain
Section B.10. Summary of Equations
Section B.11. Exercises and Projects
Unit C. Common-Emitter Amplifier Stage
Section C.1. DC (Bias) Analysis
Section C.2. Linear or Signal Model for the BJT
Section C.3. Amplifier Voltage Gain
Section C.4. Accuracy of Transistor Gain Measurements
Section C.5. Effect of Finite Slope of the Transistor Output Characteristic
Section C.6. Selection of Coupling Capacitors
Section C.7. Common-Emitter Amplifier with Active Load
Section C.8. Frequency Response of NPN – PNP Amplifier Due to the Base
Shunt Capacitor
Section C.9. Common-Emitter Stage with Emitter Resistor and the EmitterFollower Amplifier Stage
Section C.10. Summary of BJT Model Parameter Relations
Section C.11. Summary of Circuit Equations
Section C.12. Exercises and Projects
Laboratory Project 1. Basic Circuit Analysis for Electronic Circuits and
Programming Exercises
Section P1.1. Resistor Voltage-Divider Measurements
Section P1.2. Resistor Voltage Divider with Current Measurement
Section P1.3. Resistor Voltage Divider with Resistor Measurement
Section P1.4. Resistor Voltage Divider with a Sine-Wave Source Voltage
Section P1.5. Frequency Response of a Resistor-Capacitor Circuit
Laboratory Project 2. Basic NMOS Common-Source Amplifier with
Programming Exercises
Section P2.1. NMOS Common-Source Circuit with Drain Current Measurement
Section P2.2. NMOS Common-Source Amplifier with Resistor Gate Bias Circuit
Section P2.3. Amplifier with Signal and Gain Measurement
Laboratory Project 3. Characterization of the PMOS Transistor for Circuit
Simulation
Section P3.1. SPICE Parameters and Pin Diagram
Section P3.2. SPICE Equations
Section P3.3. PMOS Transistor
Section P3.4. Low-Voltage Linear Region of the Output Characteristic

Section P3.5. PMOS Parameters from the Transfer Characteristic
Section P3.6. PMOS Lambda from the Transfer Characteristic
Section P3.7. PMOS Output Characteristic
Section P3.8. PMOS Lambda
Laboratory Project 4. Characterization of the NMOS Transistor for Circuit
Simulation
Section P4.1. SPICE Parameters and Chip Diagram
Section P4.2. NMOS Transistor
Section P4.3. SPICE Equations
Section P4.4. NMOS Parameters from the Transfer Characteristic
Section P4.5. NMOS Lambda from the Transfer Characteristic
Section P4.6. NMOS Gamma SubVI
Section P4.7. NMOS Gamma
Section P4.8. NMOS Circuit with Body Effect
Laboratory Project 5. PMOS Common-Source Amplifier
Section P5.1. SPICE Equations and Pin Diagram
Section P5.2. PMOS Common-Source Amplifier DC Setup
Section P5.3. Amplifier Gain at One Bias Current
Section P5.4. Amplifier Gain versus Bias Current
Laboratory Project 6. PMOS Common-Source Amplifier Stage with CurrentSource Biasing
Section P6.1. PMOS Schematic and Pin Diagram
Section P6.2. SPICE PMOS and Circuit Equations
Section P6.3. PMOS Current-Source Amplifier DC Setup
Section P6.4. Amplifier Gain
Section P6.5. Amplifier Frequency Response
Laboratory Project 7. NMOS Common-Source Amplifier Stage with SourceResistor Bias
Section P7.1. Chip Diagram and SPICE Equation
Section P7.2. NMOS Common-Source Amplifier DC Evaluation
Section P7.3. Amplifier Gain at Optimum Bias for Linear Output
Section P7.4. Optimum Bias Stability Test
Section P7.5. Amplifier Frequency Response
Laboratory Project 8. NMOS Source-Follower Stage
Section P8.1. SPICE Equations and Pin Diagram
Section P8.2. Source-Follower DC Evaluation
Section P8.3. Source-Follower Voltage Transfer Relation
Section P8.4. Source-Follower Voltage Transfer Relation with Body Effect
Laboratory Project 9. MOSFET Differential Amplifier Stage
Section P9.1. SPICE Equations and Pin Diagram
Section P9.2. DC Evaluation of the Single-Power-Supply Differential Amplifier
Section P9.3. Determination of the PMOS Parameters
Section P9.4. Amplifier Gain Measurement
Section P9.5. Transistor Parameters and DC Imbalance
Section P9.6. Common-Mode Gain Measurement
Laboratory Project 10. Current Mirror and Common-Source Amplifier with

Current-Source Load
Section P10.1. SPICE Equations and Pin Diagram
Section P10.2. Evaluation of the Current-Source Circuit
Section P10.3. Evaluation of the Mirror-Current Circuit
Section P10.4. Evaluation of the Bias Setup
Section P10.5. Measurement of the Amplifier Gain versus Drain Current
Laboratory Project 11. Operational Amplifier with Resistor Feedback
Section P11.1. SPICE Equations
Section P11.2. Bias Circuit Setup
Section P11.3. Opamp Offset Voltage
Section P11.4. Evaluation of the Bias Balancing Circuit
Section P11.5. Evaluation of the Gain and Signal Limits with Swept Input
Section P11.6. Evaluation of the Gain with Sine-Wave and Square-Wave Signals
Section P11.7. Determination of the Opamp Frequency Response
Laboratory Project 12. Operational Amplifier Integrator and Oscillator
Section P12.1. SPICE Equations
Section P12.2. Opamp Integrator
Section P12.3. Opamp Oscillator
Laboratory Project A. Communicating with the Circuit Board Using the DAQ
Section PA.1. Sending and Receiving Voltages with the Sending and Receiving
VIs
Section PA.2. Sending and Receiving Voltages from the Front Panel
Section PA.3. Plotting Measured Samples
Section PA.4. Using the Autoranging Voltmeter
Section PA.5. Observing the Oscilloscope Output Graph
Section PA.6. Discrete Output Voltage from the DAQ
Section PA.7. Discrete Input Voltage from the Circuit Board
Section PA.8. Using the Simultaneous Sending/Receiving Function
Laboratory Project B. Characterization of the Bipolar Junction Transistor for
Circuit Simulation
Section PB.1. SPICE Parameters and Transistor Diagram
Section PB.2. SPICE Equations
Section PB.3. Diode-Connected Transistor Measurements
Section PB.4. Measurement of βDC versus the Collector Current
Section PB.5. BJT Output Characteristic Measurement
Section PB.6. Simulation of the Output Characteristic Measurement
Laboratory Project C1. NPN Common-Emitter Amplifier
Section PC.1. SPICE Equations and Pin Diagram
Section PC.2. DC Circuit Setup and Parameter Determination
Section PC.3. Amplifier Gain at One Bias Current
Section PC.4. Amplifier Gain versus Bias Current
Section PC.5. Gain-Measurement Frequency Response
Laboratory Project C2. NPN – PNP Common-Emitter Amplifier with CurrentSource Load
Section PC.6. SPICE Equations and Pin Diagram
Section PC.7. Measurement of the PNP Parameters

Section PC.8. DC Circuit Setup
Section PC.9. Measurement of the Amplifier Gain

Copyright
Library of Congress Cataloging-in-Publication Data

Ashley, Kenneth L.
Analog electronics with LabVIEW / Kenneth L. Ashley.
p. cm. — (National Instruments virtual instrumentation series)
Includes bibliographical references and index.
ISBN 0-13-047065-1 (pbk. : alk. paper)
1. Electronics. 2. Electronic circuits—Computer-aided design. 3. LabVIEW. I. Title. II.
Series.
TK7816 .A84 2002
621.381--dc21
2002072656
Editorial/production supervision: Patti Guerrieri
Cover design director: Jerry Votta
Cover designer: Nina Scuderi
Manufacturing manager: Alexis R. Heydt-Long
Publisher: Bernard Goodwin
Editorial assistant: Michelle Vincenti
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© 2003 Pearson Education, Inc.
Publishing as Prentice Hall PTR
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Kenneth L. Ashley
Analog Electronics with LabVIEW
Jeffrey Y. Beyon
Hands-On Exercise Manual for LabVIEW Programming, Data Acquisition, and
Analysis
Jeffrey Y. Beyon
LabVIEW Programming, Data Acquisition, and Analysis
Mahesh L. Chugani, Abhay R. Samant, Michael Cerra
LabVIEW Signal Processing
Nesimi Ertugrul
LabVIEW for Electric Circuits, Machines, Drives, and Laboratories

Rahman Jamal · Herbert Pichlik
LabVIEW Applications and Solutions
Shahid F. Khalid
Advanced Topics in LabWindows/CVI
Shahid F. Khalid
LabWindows/CVI Programming for Beginners
Hall T. Martin · Meg L. Martin
LabVIEW for Automotive, Telecommunications, Semiconductor, Biomedical, and
Other Applications
Bruce Mihura
LabVIEW for Data Acquisition
Jon B. Olansen · Eric Rosow
Virtual Bio-Instrumentation: Biomedical, Clinical, and Healthcare Applications in
LabVIEW
Barry Paton
Sensors, Transducers, and LabVIEW
Jeffrey Travis
LabVIEW for Everyone, second edition
Jeffrey Travis
Internet Applications in LabVIEW

Preface
This book presents a study of analog electronics as a stand-alone course or as a course to be augmented by one of the many complete undergraduate textbooks on the subject.
Theory and closely coupled laboratory projects, which are based entirely on computerbased data acquisition, follow in a sequential format. All analytical device characterization formulations are based exactly on SPICE.
In addition to traditional curricula in electrical engineering and electronics technology, the course is suitable for the practicing engineer in industry. For the engineer with a general undergraduate electronics background, for example, the course of study can provide an upgrade in basic analog electronics. Under these or similar circumstances, it can be taken as self-paced or with minimum supervision.
Two course sequences are possible, depending on the emphasis desired:





For a course that stresses MOSFET characterization and circuits, beginning with
Unit 1 and following the sequence is recommended. A brief review of relevant circuit analysis and the most rudimentary basics of electronics are presented initially, with associated projects. The projects include an introduction to
LabVIEW programming along with the measurements of basic circuits. The programming aspects are directly relevant to the thrust of the course; they emphasize the measurement of analog electronics circuits. The student is thus provided with a basic understanding of LabVIEW concepts used throughout the projects. If, on the other hand, interest is directed more toward LabVIEW and computer data acquisition, device characterization, and circuit simulation, the appropriate beginning sequence is Units A through C. The associated projects are Project A,
Projects B, Project C1, and Project C2. Project A is a programming and measurement exercise that emphasizes and explores the use of LabVIEW DAQ software, the discrete nature of analog-to-digital and digital-to-analog conversions,
LabVIEW-based voltmeters with autoranging, ac voltmeters, and simultaneous sending and receiving of waveforms initiated with a function generator. This is followed with projects on transistors and transistor circuits, which are based on the bipolar junction transistor. Although the BJT is losing ground as the most important transistor in electronics (compared to the MOSFET), its inherently more complex behavior provides for a rich array of circuit simulation formulations and design challenges. The projects include the mix of NPN and
PNP devices in a single amplifier. The transistors recommended are the complementary pair NTE 186 (2N6288) and NTE 187 (2N62xx). The transistors are rated at 3 A and are therefore almost indestructible. At the much lower current levels of the projects, device heating is negligible, which is important, as all measurements assume that the circuit is at room temperature. Also, highlevel model effects are avoided, whereas low-level effects abound.

With both approaches, all the measurement LabVIEW programs are provided. Many of the extraordinary features provided by LabVIEW are included in the programs. The programs therefore may serve additionally as a tutorial in advanced aspects of LabVIEW.
The basics of operational amplifiers and their applications are treated in two units and two projects.
The book format consists of one or more units of background material for each laboratory project. A given set of theoretical units and the associated project have a related Mathcad problems file (Problemxx.mcd) and Mathcad exercise file (ExerciseXX.mcd), relating to the theory and project, respectively. The files are also in a pdf format (ProblemXX.pdf,
ExerciseXX.pdf). A Mathcad file (ProjectXX.mcd) for evaluating the results of the projects is included with each project. Accompanying each Mathcad project file are
SPICE simulator files based on PSPICE. The SPICE models for the simulations use, in each case, the parameters for the devices obtained in laboratory projects. Since the
Mathcad projects use the exact SPICE formulations, the results from Mathcad and SPICE are identical in the case of the use of basic simulation levels.

Samples of all of the projects have been completed and are included. These provide for either demonstrations or simulated results without actually running the programs with circuits. The measured data are stored in LabVIEW graphics and can be extracted to obtain data files in the same manner as actually making the measurements. In some cases, the simultaneous taking of data, plotting and curve fitting is simulated. Units 13 and 14 are theoretical only but each has Mathcad problems on the topic of these respective units.
Special features of the lab experience are as follows:








The lab projects are based entirely on computer data acquisition using LabVIEW and a National Instruments data acquisition card (DAQ) in the computer for interfacing with the circuit board.
Each device category has an associated project for evaluating SPICE parameters in which device model parameters are obtained. Subsequent amplifier projects use the parameters in performance assessment.
No external instrumentation is required. The function generator, voltmeters, and oscilloscopes are virtual and provided by LabVIEW and a DAQ card in the computer. The projects on the current-mirror load common-source amplifier and the operational amplifier require an external power supply.
Circuits are constructed on a special circuit board. The board is connected to the computer DAQ card through a National Instruments shielded 68-pin cable. The circuit board allows expedient, error-free construction of the circuits, as connector strips for the respective output and input channels and ground are available directly on the board.

Topics included in this course treat many of the most relevant aspects of basic modern analog electronics without straying into peripheral areas. The course essentially streamlines the study of analog electronics. There is not a unit on, for example, feedback per se, but most basic types of feedback are addressed at some point. The role that the device plays in frequency response is omitted. This is consistent with the fact that to a large extent, the intension is that theory and measurements can be connected.
Students of electrical engineering or electronics engineering of today have a vast array of subjects to attempt to master; it is not reasonable to expect them to labor through a classical extensive study of the subject of analog electronics, although some basic knowledge should be required. Specialization can come at a later stage, if desired.
As mentioned, many LabVIEW features are utilized in the projects. To some extent, the goal of demonstrating the extensive array of the capabilities of LabVIEW influences the design of the various projects. This includes sending voltages (including waveforms), receiving voltages (including autoscaling), scanning, graphics, reading data files, writing data files, computations such as extraction of harmonic content of a signal, assembling data in a composite form, along with a host of array manipulation processes and data curve fitting.

References

CMOS analog circuits including applications (advanced):
Allen P., and R. Holberg. CMOS Analog Circuit Design, 1st Ed. Holt, Reinhart and
Winston, New York, 1986.
Allen P., and R. Holberg. CMOS Analog Circuit Design, 2nd Ed. Oxford University
Press, New York, 2002.
Extensive coverage of analog circuits, which includes a comprehensive discussion of feedback and frequency response (advanced):
Gray, P., P. Hurst, S. Lewis, and R. Meyer. Analysis and Design of Analog Integrated
Circuits, 4th Ed. Wiley, New York, 2001.
CMOS analog circuits (with some BJT circuits) with extensive coverage of applications
(advanced):
Johns D., and K. Martin. Analog Integrated Circuit Design. Wiley, New York, 1997.
Presentation of the physical and empirical association between semiconductor devices and their models, MOSFETs and BJTs:
Massobrio G., and P. Antognetti. Semiconductor Device Modeling with SPICE.
McGraw-Hill, New York, 1993.
General textbook on electronics (basic):
Millman J., and A. Grabel. Microelectronics, 2nd Ed. McGraw-Hill, New York, 1987.
Physical description of semiconductor devices:
Muller R., and T. Kamins. Device Electronics for Integrated Circuits, 2nd Ed. Wiley,
New York, 1986.
General textbook on electronics (basic):
Sedra, A.S., and K.C. Smith. Microelectronic Circuits, 4th Ed. Oxford University Press,
Oxford, 1998.
General treatment of analog circuits including applications (basic to advanced):
Soclof, S. Design and Applications of Analog Integrated Circuits, Prentice Hall, Upper
Saddle River, N.J., 1991.

Hardware and Software Requirements

Circuit connections to the DAQ require a cable and a facility for connecting to individual pins. An efficient system is based on a National Instruments Connector Block (CB-68LP) and a basic circuit board as shown here.

Connections to the circuit board from the connector block are made one time. The two resistors of the circuit are connected to output channels 0 and 1, respecively. Thus, for example, Chan0_out, as noted, is dedicated to the top strip on the circuit board. The bottom top strip is associated with Chan0_in, and so forth.
All of the project LabVIEW files are programmed to be consistent with the plus bus (rail),
Chan0_out, and the minus bus (rail), Chan1_out. Therefore, it is intuitively helpful to have the output channels physically connected in this fashion.
The project examples included with the book were conducted on a special circuit box that connects directly to the shielded 68-pin connector. This bypasses the connector block. A shielded cable is strongly recommended in any event. Many of the projects involve the measurement of relatively low voltage signals.
In addition, the lab projects included in the book require the following (or equivalent):






Pentium PC (or equivalent).
National Instruments DAQ PCI-MIO-16E-4.
LabVIEW 6.0i Student Edition or LabVIEW 6.0i or later version.
Mathcad Professional 2001 or later version.
National Instruments Shielded 68-pin Cable.

Semiconductor Devices and Components (Recommended)
6-Transistor (3-gate) CMOS Array – CD4007[*]

CMOS Opamp – SGS-Thomson TS271[**]
NPN - Medium-Power NPN BJT – NTE186[***]
PNP - Medium-Power PNP BJT – NTE187[****]
Capacitors
Resistors

Connector Block Pins (AT-MIO-E or PCI-E Series)
Chan0_out

Pin 21 Chan0_in Pin 68

Gnd – Pin 34

Chan1_out

Pin 22 Chan1_in Pin 33

Gnd – Pin 66

Output Channel Gnd Pin 55 Chan2_in Pin 65 - plus Pin 31 - minus
Input Channel Gnd

Pin 67 Input and output grounds are connected.

+5 V Supply Voltage Pin 14

[*]

The CD4007 chip contains three CMOS inverters or three PMOS and three NMOS transistors. Since they are inverters, NMOS and PMOS pairs have Hardware and
Software Requirements internally connected gates. However, this does not prevent having a sufficient number of the individual transistors in the analog laboratory projects.
[**]

The TS271 is chosen as it has simple external resistor biasing. Thus, students can gain an intuitive feel for the relation between the characteristics of the CMOS opamp and bias current with straightforward exchange of bias resistors. In the case of a group of students, for example, each student can select a different bias current, such that all of the results can be assembled to plot the opamp characteristics, such as gain and frequency response versus bias current. In addition, the circuitry of the opamp is straightforward and may be understood within the scope of the book. Extensive experience in our laboratory with devices has demonstrated that this opamp can withstand considerable abuse without failing even though it is a MOSFET chip. It is however, strongly advised that the power supply never be turned on until the power-supply pins, input pins and output pin are connected in the circuit.

[***]

The NTE186 is a rugged npn BJT that is investigated at current levels well below the normal operating range. Heating of the device is thus minimized and for the

measurements, it can be assumed to be at room temperature. Also, various high-level injection effects, which render the basic SPICE parameter set invalid, are avoided.
[****]

Complementary paired with the NTE186.

LabVIEW VI Libraries and Project and Problem
Folders and Files
Each project has a folder, which contains the LabVIEW library plus any related Mathcad files for that project. Mathcad files include those for the exercises and results analysis
(project files). The project folder also has circuit-simulator subfolders for Schematics and
Capture.
A LabVIEW VI library is included for each project. These are LabVIEW files with extension llb. The LabVIEW files within a library have extension vi. A given project library will contain most of the LabVIEW virtual instruments for that project. The additional VIs are in the User.lib folder, which is in the LabVIEW application folder. The
User.lib folder contains all the LabVIEW libraries and other LabVIEW files that are not included in the individual project libraries. The folders are Read_Rite, Dat_File,
FunctGen, and Subvi.
Each problem folder has a set of problems associated with the unit with the same number.
Each problem set has a pdf file (Word), a Mathcad solutions file, a pdf version on the
Mathcad file and a circuit-simulator subfolder.
There are also pdf files for the composite of the problems (WordProb.pdf), Mathcad problem-solution files (MathcadProb.pdf), project exercises (MathcadExer.pdf), project
Schematics exercises (SchematicsExer.pdf), and project Capture exercise
(CaptureExer.pdf).
The procedure for installation of the libraries from the CD onto the computer is described in the Readme files.

Unit 1. Elementary Circuit Analysis for Analog
Electronics
In this unit, we present a basic review of segments of circuit analysis which recur repeatedly in electronic circuits. A firm grasp on these is essential to developing an understanding of the analysis and design of basic electronic circuits. A transistor is included in the circuits to show a correlation between circuit analysis and electronics.
Only steady-state circuit situations are considered here. This includes dc and sinusoidal.
Some transient analysis is considered in connection with operational amplifier applications with capacitors.

1.1. Resistor Voltage Divider and MOSFET DC Gate Voltage
Figure 1.1(a) shows a basic NMOS amplifier stage. This is the dc (or bias) portion of the circuit, which excludes the signal part. The terminals of the transistor are designed G
(gate), D (drain) and S (source). The design calls for a dc voltage VG, with respect to the zero reference voltage, which is obtained by dividing the supply voltage VDD between bias resistors RG1 and RG2. Since the gate terminal has zero current, the voltage, VG, at the gate can be assessed with the resistor network separated from the circuit as in Fig. 1.1(b).
The goal is to relate the node voltage VG to the values of RG1 and RG2 and VDD. The result is the basic resistor voltage-divider relation.

Figure 1.1. (a) Dc circuit for the basic NMOS amplifier. (b) Circuit for determining the gate voltage, VG.

Note that since VDD is given with respect to the reference zero volts, the VDD designation at the top node is equivalent to the supply voltage, also referred to as VDD. The current
IRG is
Equation 1.1

The voltage across the resistor RG2 is VG (since VG is with respect to the zero reference) and this is
Equation 1.2

It can be concluded that the gate voltage is the value of RG2 divided by the sum of the two gate-bias resistors.

1.2. Output Circuit and DC Drain Voltage
For the dc circuit in Fig. 1.1, the drain voltage is determined from
Equation 1.3

As illustrated in Fig. 1.2, for the purpose of a solution to (1.3), the transistor can be replaced by a current source as shown in Fig. 1.2. Drain current ID is a function of VG; that is, ID = f(VG). Thus, in a design, the value of VG determines the value of VD. ID is related to VG according to
Equation 1.4

Figure 1.2. Circuit for illustrating the determination of the drain voltage, VD.

This relation and parameters Vtno and kn are discussed in Unit 2.

1.3. Frequency Response of the Amplifier Stage
Capacitance associated with amplifiers may cause the output to fall off at low and high frequencies. This effect is referred to as the frequency response of the amplifier. A generalization of possible capacitance is shown in the circuit of Fig. 1.3. Capacitor Cg is an external capacitance, which is included to attach a sine-wave signal source, consisting of Vsig (e.g., sine-wave peak) and Rs, without interrupting the dc bias circuitry. Similarly, there could be an output capacitance, which couples the signal output voltage to an external load resistor. Capacitor CT is associated with the internal capacitance of the transistor. It may be regarded as an equivalent effective capacitance that represents all of the capacitance of the transistor.
Figure 1.3. Amplifier including possible circuit capacitance.

Generally, the frequency range over which a given capacitor is effective is much different for the two capacitors. Capacitor Cg affects the output at low frequencies, while the effect of CT is realized at the high end of the spectrum. Thus, their effects can be considered separately if, as assumed in the following, the high and low ends of the response function are widely separated in frequency, that is, by several orders of magnitude.
Figure 1.4 shows the signal circuits for the two cases of low (a) and high (b) frequencies.
As discussed in Unit 2, the signal circuit is formulated from the complete circuit by setting all dc voltages to zero. This includes, for this amplifier, the power supply and dc voltage across the capacitor Cg. Note that the transistor plays no apparent role in the frequency response in the equivalent circuit. It is, of course, critically important in dictating the value of CT.
Figure 1.4. Circuits for low (a) and high (b) frequencies.

The two circuits, (a) and (b), are technically high-pass and low-pass circuits, respectively.
In combination, they have a midband range, which is the normal range of frequency for operation of the amplifier. As mentioned above, if the midband separates the low and high portions by a sufficient range of frequency, the effects may be considered separately, as suggested in Fig. 1.4.
The response function is obtained by considering the frequency dependence of the node voltage Vg(f) for the constant-magnitude sine-wave source voltage, Vsig. (Since the only voltages under consideration in the circuits of Fig. 1.4 are those associated with signals, lowercase subscript is used. This is discussed further in Unit 2.)
The frequency response is first considered for the low end of the spectrum and involves
Cg only, as in the circuit of Fig. 1.4(a). We can utilize the voltage-divider relation obtained above as (1.2). For this case this is
Equation 1.5

where RG = RG1 || RG2.
Using the definitions
Equation 1.6

and

Equation 1.7

the result is condensable to
Equation 1.8

The magnitude is
Equation 1.9

At f = flo,
. This, by definition, is the response magnitude for the 3-dB frequency, f3dB, for the low-frequency end of the response function. That is, in general, f3dB is the frequency at which the response falls to
(for decreasing frequency) from the maximum, asymptotic value. Thus, for the simple case here of one capacitor, f3dB = flo.
The equation for the response function associated with CT is similar to (1.8) and is
Equation 1.10

where

Equation 1.11

The frequency f3dB for this case is just fhi. The frequency response of circuits of the type of Fig. 1.4 is measured in Project 1. In the design of the project circuits, capacitors and resistors are selected to give widely different flo and fhi values.

1.4. Summary of Equations
Resistor-circuit voltage divider.

Drain current and gate voltage relation.
Low-frequency frequency-response function. High-frequency frequency-response function. Midband magnitude of the signal gate voltage. 1.5. Exercises and Projects
Project Mathcad
Files

Exercise01.mcd - Project01.mcd

Laboratory Project 1 Basic Circuit Analysis for Electronic Circuits and Programming
Exercises
P1.1

Resistor Voltage-Divider Measurements

P1.2

Resistor Voltage Divider with Current Measurement

P1.3

Resistor Voltage Divider with Resistor Measurement

P1.4

Resistor Voltage Divider with a Sine-Wave Source Voltage

P1.5

Frequency Response of a Resistor-Capacitor Circuit

Unit 2. Transistors and Voltage Amplification

Radio transmitters and receivers have existed since before the end of the nineteenth century. A practical form of wireless telegraph, attributed to G. Marconi, appeared in
1895, and successful transmission across the Atlantic Ocean was achieved in 1901.
However, in the early part of the twentieth century, systems were limited by the lack of a means of voltage amplification. The appearance of a voltage amplification device, the vacuum tube, dramatically improved the concept, as microvolt signals could be boosted for receiving and transmitting.
In the middle of the twentieth century, the transistor appeared. The idea of transistors based on a sandwich of pn junctions (BJT) and a field-effect transistor based on pn junctions (JFET) and on a metal – oxide – semiconductor (MOS) structure (basically, a capacitor) were all understood at the time. However, pn-junction devices became a practical realization much sooner than the MOS structure, due to fabrication complications in producing the MOS device as well as perhaps a perceived lack of need.
The JFET served as an interim field-effect transistor until the MOS technology evolved.
It provided for a transistor with very high input resistance and was used extensively as the input transistors for BJT opamps.
A textbook on radio, Elements of Radio, published in 1948 (Marcus and Marcus, 1948), makes no mention of transistors. A 1958 text, (Millman, 1958), Vacuum-Tube and
Semiconductor Electronics, gives equal weight to vacuum tubes and BJTs in electronic circuits but makes no mention of the field-effect transistor. Slightly later (Nanavati, 1963), in An Introduction to Semiconductor Electronics, as the title suggests, vacuum tubes are dropped completely and the only reference to a field-effect transistor is in one section of the last chapter and this refers to a junction field-effect transistor. In 1965, in his textbook
Analysis and Design of Electronic Circuits, Chirlian devotes a small portion of the book to vacuum tubes, but most of the emphasis is on circuits based on the BJT (Chirlian,
1965). No mention is made of the field-effect-transistor. An example of a book in which
BJTs and field-effect transistors of both types were finally given balanced treatment was published in 1979 (Millman, 1979). Textbooks tend to lag the industry a bit, and during the 1970s, MOSFET circuits were emerging rapidly, driven by the simultaneous development of integrated circuits. The four editions of a text on analog circuits by Gray and Meyer, (1977, 1984, 1993) and Gray, et al. (2001) serve well as a series through which we observe a transition from mostly BJT to, in the last two editions, more-or-less equal treatment of BJT and MOSFET devices. A recent textbook on the subject of analog integrated circuits (Johns and Martin, 1997) takes the approach that such circuits are now totally dominated by MOSFETS but includes some BJT applications. BiCMOS, a combination of MOSFET and BJT devices on the same integrated circuit, is growing in popularity as more ways of taking advantage of the superior properties of the two transistor types are developed.
Since the earliest transistors, there has been persistent competition between BJT and
MOS transistors. It has been, to a large extent (along with many other considerations), a matter of power consumption versus speed; the BJT has been faster but is associated with high power consumption. The MOSFET has gradually taken over as the most important transistor, with increased emphasis on integrated circuits and improved speeds.

2.1. BJT and MOSFET Schematic Symbols, Terminal Voltages, and
Branch Currents
The BJT can be either a pnp or an npn. The MOSFET similarly can be a pmos or an nmos.
The equivalents are npn and nmos and pnp and pmos. The following discussion is based on the npn and nmos, as shown in Fig. 2.1. (All polarities and current directions are reversed for the pnp and pmos. This provides for important versatility in applications.)

Figure 2.1. BJT npn and MOSFET nmos transistors. The terminal configurations are designated common emitter and common source.

The BJT terminals are designated collector, base, and emitter while those of the
MOSFET are drain, gate, and source. The terminal configurations in Fig. 2.1 are, for the
BJT, the common emitter, and for the MOSFET, the common source, in amplifier-stage parlance. This suggests that both the input (left side) and output (right side) are referred to the common terminal. For example, for the BJT, the input terminal voltage is VBE and the output terminal voltage is VCE. Similarly, for the MOSFET, we have VGS and VDS.
Note that in the convention of subscripts in electronics, the first subscript is assigned positive. This matches the assignments in the diagram, and the plus and minus signs are superfluous. Note also the convention for symbols for all currents and voltage.
Total voltage and current: vXY, iX
Dc, bias, quiescent, or operating point: VXY, IX
Signal or ac (RMS, peak): Vxy, Ix
General instantaneous signal: vx, ix
The voltage and current symbols in Fig. 2.4 are therefore for dc. For a voltage, a single subscript means that this terminal (or node) voltage is referred to the common terminal.
For example, in the npn case above, VCE = VC.

Figure 2.4. Basic NMOS amplifier with resistor gate biasing and input signal Vs.
(a) Complete circuit. (b) Signal (or ac or incremental) circuit. The signal circuit

is obtained by setting the power supply (dc) node to zero volts. (c) Linear signal circuit replaces the linear schematic representation.

The input terminals vBE and vGS are the control terminals; that is, they control the output currents iC and iD. In both cases, the terminal pairs possess extremely nonsymmetrical voltage – current behavior. With the polarities as shown, the currents flow readily, whereas with the opposite polarities, the output currents are cut off or are, for most purposes, essentially zero.
The basic (simplified) general relations between the currents and voltages are:
Equation 2.1

Equation 2.2

IS, VT, kn, Vtn, and VT are device model parameters or physical constants.
In linear circuit applications, for example, as amplifier stages, the transistors are provided with a circuit configuration that sets up dc, or bias, currents and terminal voltages
(sometimes referred to as the Q-point, for quiescent, or in SPICE, the operating point). In the amplifier application, a signal voltage is applied to the input, that is, superimposed on the dc magnitude, which must be much smaller than the dc voltage if the signal inputoutput relation is to be linear. This is apparent from (2.1) and (2.2), which are nonlinear relations. All of the currents and terminal voltages will change in response to the input signal, and all of these incremental changes must be small compared to any of the dc currents or voltages, in order for the linear relationships to be valid.
In circuit applications, both types of transistors are operated in all three possible terminal configurations. This provides for a wide variety of amplifier-stage characteristics, including gain and input and output impedance.

2.2. Fundamentals of Signal Amplification: The Linear Circuit
The most fundamental property of a useful electronic voltage amplification device is that it possess a transconductance that leads to the possibility of voltage gain.
Transconductance is defined as the ratio of the signal (ac, incremental) current out, iout δiOUT, and the applied input signal voltage, vin δvIN. That is, transconductance gm is
Equation 2.3

For the BJT, iOUT iC and vIN vBE, while for the NMOS, iOUT iD and vIN vGS. Thus,
(2.1) and (2.2) can be used for the BJT and MOSFET, respectively, to obtain an expression for gm. The results are
Equation 2.4

and

Equation 2.5

IC and ID are the dc (bias) currents of the transistors, so for comparison they can be made equal. At room temperature, the thermal voltage is VT = 26 m. For the MOSFET, VGS is the gate – source bias voltage and Vtn is the transistor threshold voltage. The difference, as in the denominator of the transconductance expression, could typically be about VGS –
Vtn = 500 mV.
The expression (2.3) suggests the linear model given in Fig. 2.2. Included in the model is an input resistance, rin, which accounts for the fact that there can be an incremental current flowing into the input terminal for an increment of input voltage. The model applies in general to amplifying devices, including the vacuum tube (VT), BJT, JFET, and MOSFET. There exists a wide range of magnitude of transconductance and input resistance between the devices. The input resistance, though, affects only the loading of the input signal source; otherwise, the relation of (2.3) applies in all cases, and the transconductance is the key to the gain for a given device type. The input resistance is essentially infinite for the vacuum tube and the MOSFET (common source) but can be as low as a few ohms in some configurations for the BJT (e.g., common base).

Figure 2.2. Basic linear model of a voltage amplification device. Model parameters are gm and rin.

It is interesting to compare the transconductance of the BJT and MOSFET along with the vacuum tube. We will make a comparison at ID = IC = 10 mA (suitable for a vacuum tube) even though transistors would not usually be operated at such high currents, especially in an integrated circuit. Consulting a source of information for a triode 6SN7 (perhaps one of the most common tubes of all time), one deduces from a graphical analysis the plate characteristics that, for example, gm(VT) = 3 mA/V. From (2.4) and (2.5), we obtain gm(BJT) = 385 mA/V and gm(MOSFET) = 40 mA/V with VGS – Vtn = 500 mV. The BJT is decidedly superior in this respect, and this is one of the factors contributing to the sustained life of the transistor in industry. That is, the BJT amplifier stage can potentially have a much higher voltage gain. The vacuum tube is clearly inferior to both transistors

and points to the reason for the need for so many amplification stages in some VT amplifiers. The output voltage of amplifiers based on any of the devices will depend on the value of the load resistance, RL, which is added to the circuit of Fig. 2.2 in Fig. 2.3. Note that, in general, RL is not necessarily an actual resistor but could be an effective resistance, as dictated by the amplifier circuitry that is connected to the output of a given stage, combined with a bias resistor. The output voltage induced across RL will be
Equation 2.6

Figure 2.3. Basic linear model of a voltage amplification device with load RL connected. The minus sign is a result of the current flowing up through RL. The signal voltage gain is the incremental output voltage divided by the incremental input voltage such that the gain can readily be obtained from (2.6) as
Equation 2.7

Thus, the gain is directly related to the parameter gm for a given transistor. In general, av can be positive or negative, depending on the terminal configuration. For example, the common base (BJT) and common gate (MOSFET) are positive (noninverting) gain amplifiers. 2.3. Basic NMOS Common-Source Amplifier
An example of the application of the transconductance relation for the transistor is the basic circuit in Fig. 2.4. Setting dc voltages (in this case, VDD) equal to zero in Fig. 2.4(a) leads to the signal (or ac) circuit [Fig. 2.4(b)]. This follows from the fact that the signal circuit involves only incremental variables (changes) and VDD is a constant.
The schematic symbol for the transistor in the signal circuit associates the output current with the input voltage according to the linear relation of (2.3). For linear circuit analysis, the linear equivalent circuit of Fig. 2.2 (Fig. 2.4(c)) replaces the linear schematic-symbol representation [Fig. 2.4(b)]. For the MOSFET, rin is infinite and therefore omitted.
The overall gain from the signal source to the output is av = Vo/Vs, which is
Equation 2.8

where Vo/Vg is (2.7) and Vg/Vs is provided by the simple resistor-divider relation given in
(1.2).

2.4. Transistor Output Resistance and Limiting Gain
The linear-equivalent circuit of Fig. 2.2 includes an idealization in that the output is a pure current source. In real transistors, the collector (BJT) or drain (MOSFET) current increases with increasing VCE or VDS. This is accounted for by including an output resistance, rout, in the linear model, as added to the circuit in Fig. 2.5. For the BJT and
MOSFET, respectively, the value of rout is
Equation 2.9

Equation 2.10

Figure 2.5. Basic linear circuit with transistor linear model. Circuit includes signal source voltage and load RL, Transistor model now includes output resistance rout.

where VA is the characterizing transistor parameter. Note that this voltage dependence is not included in (2.1) and (2.2); these equations are consistent with the simplified circuit model of Fig. 2.2. Similarly, the voltage dependence will alter gm from the simple forms of (2.4) and (2.5). This is discussed in Unit 4.
The actual gain, with a load RL, which includes the output resistance, can be obtained from modification of (2.7) to include rout in parallel with RL as in Fig. 2.5. The result is
Equation 2.11

The parameter VA of both transistors can typically be about 100 V. (In MOSFETs, the parameter is usually referred to as λ, which is the reciprocal, λ = 1/VA.) A useful comparison between the devices is the maximum limiting gain of the common-emitter
. The and common-source amplifier voltage gains, which applies for the case of RL gain in this case is
Equation 2.12

Using (2.4), (2.5), (2.9), and (2.10), we obtain for the limiting gain:
Equation 2.13

Equation 2.14

Using sample numbers from above, the comparison gives av lim(BJT) –4000 and av
–400. The vacuum tube, type 6SN7, has a typical output resistance rout lim(MOSFET) rp 7KΩ (p for plate), which leads to a limiting gain magnitude of about 21. (This is referred to as the μ of the tube.) You have to respect the amplifier designers of the vacuum-tube era when considering what was accomplished despite the limitations of these amplifying devices.
In modern integrated circuits, it is possible to implement load circuits, which have an effective RL >> rout such that the limiting gain can be achieved. This is particularly important in MOSFET amplifiers to make up for the relatively low value of gm.

2.5. Summary of Equations
BJT transfer function and transconductance relation. MOSFET transfer function and transconductance relation.
General voltage-gain relation from the transistor input. Gain relation from the signal source.

General relation for the transistor output resistance. Voltage gain, including the effect of the transistor output resistance.

2.6. Exercises and Projects
Project Mathcad
Files

Exercise02.mcd - Project02.mcd

Laboratory Project 2 Basic NMOS Common-Source Amplifier with Programming
Exercises
P2.1

NMOS Common-Source Circuit with Drain Current Measurement

P2.2

NMOS Common-Source Amplifier with Resistor Gate Bias
Circuit

P2.3

Amplifier with Signal and Gain Measurement

2.7. References to the Electronics Book Sequence
Chirlian, P. M. Analysis and Design of Electronic Circuits. McGraw-Hill, New York,
1965.
Gray, P. R. , and R. G. Meyer . Analysis and Design of Analog Integrated Circuits, 1st,
2nd, and 3rd eds. Wiley, New York, 1977, 1984, and 1993.
Gray, P. R. , P. J. Hurst , S. H. Lewis , and R. G. Meyer . Analysis and Design of Analog
Integrated Circuits, 4th ed. Wiley, New York, 2001.
Johns, D. , and K. Martin . Analog Integrated Circuits. Wiley, New York, 1997.
Marcus, A. , and W. Marcus . Elements of Radio, 2nd ed., Prentice-Hall, New York,
1948.
Millman, J. Vacuum-tube and Semiconductor Electronics. McGraw-Hill, New York,
1958.
Millman, J. Microelectronics. McGraw-Hill, New York, 1979.
Nanavati, R. P. An Introduction to Semiconductor Electronics. McGraw-Hill, New York,
1963.

Unit 3. Characterization of MOS Transistors for
Circuit Simulation
In this unit, the basic (Level 1 SPICE) dc MOSFET characteristic equations are introduced. The amplifier exercises and projects use the results for design and analysis.
Circuit solutions are compared with measured results from the circuit to make an assessment of the degree to which the transistor models for the MOSFET represent actual device behavior. The parameters for this unit are presented in Table 3.1. Note that in the

case of KP, we can only measure K and would be able to extract KP only if gate width W and length L were known.
TABLE 3.1
SPICE Name

Math symbol

Description

VTO

Vtno, Vtpo

Zero-bias threshold voltage.

KP

Transconductance parameter.

Gamma

γn, γp

Body-effect parameter.

Phi

2ΦF

Surface inversion potential.

Lambda

λn, λp

Channel length modulation.

3.1. Physical Description of the MOSFET
A diagrammatic NMOS is shown in Fig. 3.1. The device consists of a three-layer structure of metal–oxide–semiconductor (MOS). A two-terminal MOS structure
(connections to metal and semiconductor) is essentially a parallel-plate capacitor. In the same manner as for a normal capacitor, when a positive gate voltage, VG, is applied with respect to the p-type body (for NMOS) [i.e., with respect to the metal contact on the underside of the p-type semiconductor body (or substrate)], negative charges are induced under the oxide layer in the semiconductor. When VG (with respect to the semiconductor body) exceeds the threshold voltage, Vtno, a channel of free-carrier electrons forms under the oxide; that is, the onset of the channel occurs when VG = Vtno. The substrate is n type for the PMOS and the channel is made up of free-carrier holes.

Figure 3.1. MOS transistor consisting of a metal – oxide – semiconductor layered structure (plus a metal body contact on the bottom). A positive gate voltage, VG > Vtno, induces a conducting channel under the oxide, which connects the two n regions, source and drain. All voltages are with respect to VB, that is, the body (substrate) of the transistor. (a) No channel; (b) uniform channel; (c) channel is just pinched off at the drain end of the channel; (d) channel length is reduced due to drain pn-junction depletion region extending out along the channel.

An n-channel MOSFET device is then completed by fabricating n regions, source and gate, for contacting the channel on both ends of the channel. For VG < Vtno [Fig. 3.1(a)] there is no channel under the oxide, and the two n regions are isolated pn junctions. When
VG > Vtno and source voltage, VS, and drain voltage, VD, are both zero (all with respect to the body) [Fig. 3.1(b)] a uniform-thickness n-type channel exists along the length of the oxide layer and the source and drain regions are connected by the channel. Thus, the channel is a voltage-controlled resistor where the two ends of the resistor are at the source and drain and the control voltage is applied at the gate.
In electronic circuit applications, the terminal voltages are referred to the source; gate and drain voltages are designated as VGS and VDS (NMOS). In analog circuits, VGS > Vtno (in order for a channel to exist), VDS is positive, and a drain current flows through the channel and out by way of the source (and the gate current is zero). On the drain end of the channel, the voltage across the oxide layer is VGD = VGS – VDS. The channel at the drain end just shuts off when VGD = Vtno. VDSsat = VGS – Vtno [Fig. 3.1(c)] is defined for this condition as the saturation voltage. The transistor is referred to as in the linear (or triode) region or active region for VDS < VDSsat and VDS > VDSsat, respectively.
For VDS > VDSsat (active mode of operation), the channel length decreases from L to L' as the reverse-biased depletion region of the drain pn junction increases along the channel
(along the oxide – semiconductor interface) [Fig. 3.1(d)]. The increment VDS – VDSsat drops across the depletion region of the drain pn junction. In long-channel devices, the reduction of channel length is relatively small compared to the channel length. In this case, the length is roughly a constant and the channel resistance, for a given VGS, is independent of VDS.

From a circuit point of view, for VDS >> VDSsat, by Ohm's law,
Equation 3.1

where Rchan(VGS) is the resistance of the channel and is a function of VGS. Assuming that
L' L, for a given VGS, Rchan(VGS), and thus ID, is approximately a constant for VDS
VDSsat. Thus, the drain, in circuit terms, appears like a current source. In many modern
MOSFET devices, this is only marginally valid. In the following, the definition Veffn
VDSsat = VGS – Vtno will be used. (The subscript is an abbreviation for effective.) The
PMOS has a counterpart, Veffp VSDsat = VSG – Vtpo. Veffp is a frequently recurring term in device and circuit analytical formulations.

3.2. Output and Transfer Characteristics of the MOSFET
The equations used in the following to characterize the MOSFET transistor are from the
SPICE Level 1 model. SPICE also has more detailed models in Level 2 and Level 3.
These can be specified when running SPICE. However, the number of new model parameters, in general, in circuit simulation is practically boundless. Level 1 is chosen here as it is the most intuitive, that is, the most suitable for an introductory discussion of device behavior. Some new models, for example, which focus on frequency response at very high frequencies, can include pages of equations. In addition, Level 1 is suitable and adequate for many examples of circuit simulation.
The basic common-source NMOS circuit configuration is repeated in Fig. 3.2. Here it serves as a basis for discussing the dc SPICE parameters of the MOSFET transistor. In the example, VDS = VDD. The output characteristic is a plot of ID versus VDS for VGS = const. A representative example is shown in Fig. 3.3. As mentioned, the low-voltage region is referred to as the linear region, triode region, or presaturation region. Outside this region for higher voltages is the active (saturation) region. This is referred to here as the active region to avoid confusion with the fact that the nomenclature is just the opposite in the case of the BJT; that is, the low-voltage region is called the saturation region. As discussed in Unit 3.1, the linear and active regions are delineated by Veffn
VDSsat = VGS – Vtno.

Figure 3.2. Common-source circuit configuration for discussion of the dc model parameters of the NMOS transistor. The three-terminal transistor symbol implies that the body and source are connected.

Figure 3.3. Mathcad-generated output characteristic for the NMOS transistor.
The plot illustrates the linear and active regions. The linear region is also called the triode region or presaturation region. Current is in microamperes and Veffn =
0.8 V. Also plotted is the ideal characteristic with zero slope in the active region.

The output-characteristic equation in the linear region corresponds to VDS ranging from the condition of Fig. 3.1(b) to that of Fig. 3.1(c). As VDS increases from zero, the channel begins to close off at the drain end (i.e., the channel becomes progressively more wedge shaped). The result is an increase in the resistance of the channel as a function of VDS, and therefore a sublinear current – voltage relation develops.
When VGS > Vtno, the electron charge in the channel can be related to the gate voltage by
Qchan = Cox(VGS – Vtno) (per unit area of MOSFET looking down at the gate), where Cox is the parallel-plate capacitance (per unit area) formed by the MOS structure. This provides a simple linear relation between the gate voltage and the charge in the channel.
The conductivity in the channel is σchan = μnQchan/tchan, where μn is the mobility of the electrons in the channel and tchan is the thickness of the channel into the semiconductor.
0), the channel conductance is
Thus, in the case of a uniform channel (i.e., for VDS
Equation 3.2

where
Equation 3.3

and where KPn = μnCox is the SPICE transconductance parameter (the n subscript is the equation symbolic notation for the NMOS; the parameter in the device model is just KP),
W is the physical gate width, and L, again, is the channel length. Parameter KPn is related to the electron mobility in the channel and the oxide thickness. Therefore, it is very specific to a given MOSFET device.
As VDS increases, but is less than Veffn [transition from Fig. 3.1(b) to 3.1(c)], the wedgeshaped effect on the channel is reflected functionally in the channel conductance relation as Equation 3.4

This leads to an output characteristic equation for the linear region, which is
Equation 3.5

The derivation leading to (3.4) and (3.5) is given in Unit 3.4. The linear-region relation,
(3.5), is applicable for VDS up to VDS = Veffn, which is the boundary of the linear and active regions. The active-region equation is then obtained by substituting into (3.5), VDS
= Veffn, giving

Equation 3.6

This active-region current corresponds to the zero-slope ideal curve in Fig. 3.3. As discussed in Unit 3.1, the drain current is not actually constant in the active region (in the same manner as for a BJT), due to the fact that the physical length of the channel is reduced for increasing VDS beyond VDS = Veffn. The reduction in the channel length has the effect of slightly reducing the resistance of the channel. This is taken into account using the fact that kn 1/L, from (3.3), where L is the effective physical length between the source and drain regions. For VDS > Veffn, a reduced length L' = L(1 – λnVDS) is defined which leads to a new effective

,

Equation 3.7

where λn is the SPICE channel-length modulation parameter (Lambda). Substituting for kn in (3.6) produces
Equation 3.8

(Note: A preferred form would be ID = kn Veffn2[1 + λn (VDS – Veffn)] because the channellength effect only begins for VDS > Veffn and kn could be defined properly for effective length L at VDS = Veffn. Level 1 SPICE uses (3.8).)
Level 1 SPICE also applies this channel-length reduction factor to the equation in the linear region, (3.5). To match the linear-region equation to the active-region equation,
(3.5) becomes, at the edge of the active – linear regions,
Equation 3.9

and, in general
Equation 3.10

[Again, the fact that the channel length is not reduced with the transistor in the linear region would suggest the use of (3.9) throughout the linear region. Level 1 SPICE uses
(3.8) and (3.10).]
In general, Vtn is a function of the source-body voltage, VSB. We assume for the moment that VSB = 0. This applies, for example, to the common-source circuit in Fig. 3.2, since the body will always be at zero volts, and the source in this case is grounded as well. For this case, Vtn = Vtno, as used above. In laboratory projects we measure the output characteristic from which parameter λn can be obtained. This is based on (3.8). The I – V slope in the active region is
Equation 3.11

From the data measured, a straight-line curve fit determines the slope and the zero VDS intercept (ID at VDS = 0). These are used in (3.11) to obtain λn from λn = slope/intercept.
The intercept is the extension of the active region of Fig. 3.3 (dashed line) to the ID axis.
When applying the equations of this development to the PMOS, the voltage between the gate and source is defined as positive with respect to the source, that is, VSG. To be consistent, the threshold voltage for the PMOS, Vtp, is also positive. In the SPICE model, however, the threshold voltage is assigned negative because positive is taken for both types of devices with respect to the gate (VGS is negative for the PMOS), and the threshold voltage for the PMOS is negative.
The transfer characteristic is obtained by holding VDS constant and varying VGS. In the
MOSFET parameter-determination experiments of Projects 3 and 4, we plot VGS versus for the transistor biased into the active region. The equation is
Equation 3.12

where

is (3.7)

The slope in (3.12) is and the zero intercept is expected to be Vtno. LabVIEW obtains the slope and intercept from a straight-line fit to the data. The measured transfer characteristic thus yields the two parameters

and Vtno.

In Project 4, parameter λn is obtained from finding based on

at two different VDS values. This is

Equation 3.13

where the

values are measured and λn is the only unknown.

3.3. Body Effect and Threshold Voltage
In Fig. 3.4 is shown an example of a circuit in which the body and source cannot be at the same voltage. We now use the four-terminal symbol for the NMOS, which includes the body contact. In most applications, the body would be tied to the lowest potential in the circuit (NMOS), in this case, VSS (e.g., VSS = –5 V). But by the nature of the circuit, the source voltage is VS = VSS + IDRS, such that the source-body voltage is VSB = IDRS.

Figure 3.4. NMOS transistor circuit with a resistor, RS, in the source branch.
With the body attached to VSS, VSB = IDRS.

In MOSFET devices, the threshold voltage depends on VSB and in SPICE is modeled according to (NMOS)
Equation 3.14

SPICE parameters contained in the equation are Vtno (VTO), γn (Gamma), and 2ΦF (Phi)
(Table 3.1). Typically, γn 0.5 V1/2 and 2ΦF 0.6 V. Therefore, for example, for VSB =
5 V, the body effect adds 0.8 V to Vtno.
In the case of the CMOS array ICs of our lab projects (CD4007), the body effect for the
PMOS is significantly less pronounced than for the NMOS (γp < γn), but the parameter for the channel-length-modulation effect is much smaller for the NMOS than for the PMOS
(λn < λp). The combination suggests that the chip is a p-well configuration; that is, the
NMOS devices are fabricated in "wells" of p-type semiconductor that are fabricated into an n-type substrate. The PMOS devices reside directly in the n-type substrate material.
As far as our measurements are concerned, the extremes in parameters are an advantage, as we are interested in observing the effects of the various parameters.
In Project 4, a number for γn is obtained by measuring Vtn as a function of VSB. The results are plotted as Vtn versus
. LabVIEW calculates the X variable. The data plotted should give a straight line with slope γn. The effectiveness of
SPICE modeling for representing the behavior of the transistor in a circuit is investigated in Project 4. The transfer characteristic, VGS versus ID, is measured for a circuit of the type shown in Fig. 3.4, where the circuit has VSB = IDRS. In the project, VSS is swept over a range of values to produce a range of ID of about a decade. From (3.14), the threshold voltage characteristic that includes the body effect is
Equation 3.15

The input circuit loop equation (Fig. 3.4) is
Equation 3.16

Including the body effect, VGS is now [from (3.12)]
Equation 3.17

where, for this special case, VDS = VGS (VD = 0, VS = 0).
A solution is obtainable through combing (3.14), (3.16), and (3.17) for ID and VGS. These equations contain every parameter from this discussion of MOSFET SPICE parameters along with RS. In a project Mathcad file, Project04.mcd, a solution is obtained to provide a comparison with the measured VGS versus ID for the circuit. The Mathcad iteration formulation is, from (3.16),
Equation 3.18

and, from (3.15) and (3.17),
Equation 3.19

ID and VGS are found for the range of VSS corresponding to that used in the measurement, which is 2.5 < |VSS| < 10 V.

3.4. Derivation of the Linear-Region Current – Voltage Relation
The voltage along the channel is defined as Vc(x) (Fig. 3.5), with the range 0 at x = 0
(source) to Vc(L) = VD (drain). The device is in the linear-region mode, that is, VD < Veffn.
The charge in the channel at x is
Equation 3.20

where the charge at the source is Qchan = Cox(VGS – Vtno), as in the case of (3.2).

Figure 3.5. Diagrammatic NMOS transistor biased into the linear region.

A generalization of (3.2) for the incremental conductance, dGchan(x), at x over a length dx is Equation 3.21

The voltage drop across the length dx, for a drain current ID, is
Equation 3.22

where Rchan(x) = 1/Gchan(x). Using (3.21), the incremental voltage across dx is
Equation 3.23

Rearranging the equation and integrating gives
Equation 3.24

which leads to the result (3.5), repeated here

3.5. Summary of Equations
Equations for NMOS. For PMOS, reverse the order of subscripts and define ID out of the drain. Current – voltage relation for the linear region.

Current – voltage relation for the active region.

Threshold-voltage dependence on source-body voltage. 3.6. Exercises and Projects
Project Mathcad Files Exercise03.mcd - Project03.mcd - Exercise04.mcd,
Project04.mcd
Laboratory Project 3

Characterization of the PMOS Transistor for Circuit Simulation

P3.4

Low-Voltage Linear Region of the Output Characteristic

P3.5

PMOS Parameters from the Transfer Characteristic

P3.6

PMOS Lambda from the Transfer Characteristic

P3.7

PMOS Output Characteristic

P3.8

PMOS Lambda

Laboratory Project 4

Characterization of the NMOS Transistor for Circuit Simulation

P4.4

NMOS Parameters from the Transfer Characteristic

P4.5

NMOS Lambda from the Transfer Characteristic

P4.6

NMOS Gamma SubVI

P4.7

NMOS Gamma

P4.8

NMOS Circuit with Body Effect

Unit 4. Signal Conductance Parameters for Circuit
Simulation
The basic low-frequency linear model for a MOS transistor has three conductance parameters: the transconductance parameter, gm, the body-effect parameter, gmb, and the output conductance parameter gds. They are the proportionality constants between incremental variables of current and voltage. For the linear model to be valid, the increment must be small compared to the dc (bias) value of the variable. To qualify as small, the increment must be sufficiently small, in each case, as to avoid unacceptable degrees of nonlinearity in the variable relationships. The conditions are explored in Unit
5 in connection with linearity of an amplifier gain function.
In the following, the three conductance parameters are explored, and in each case, an expression for obtaining the circuit value is developed. The discussion is based on a standard amplifier stage to provide for an association with electronic circuits.

4.1. Amplifier Circuit and Signal Equivalent Circuits
To serve as an illustration of the utility of the parameters, the discussion of the linear model and g parameters will be accompanied by a signal-performance evaluation of an
NMOS transistor in the most general amplifier configuration (Fig. 4.1). The circuit includes drain and source resistors, and input is at the gate terminal. As shown in Fig.

4.1(b), output can be at the drain (common-source amplifier) or source (source-follower amplifier). Figure 4.1. (a) Ideal NMOS in a basic common-source amplifier circuit (output,
Vocs). Dc supply nodes of Fig. 4.1(a) are set to zero volts to obtain the signal circuits of Fig. 4.1(b) and (c). An alternative output is Voef [shown in (b)], which is the source-follower amplifier stage. Voltage variable Vg is the input for both cases. Figure 4.1 shows the dc (bias) circuit (a) and signal circuit (b). Replacing all dc nodes with signal ground and replacing the dc variables with signal variables as in Fig. 4.1 produces the signal circuit. It will be assumed that the schematic symbol for the transistor in signal circuit (b) is equivalent to the ideal, intrinsic linear model of the transistor. The total drain current of the model is Id = gmVgs, as, for example, in the basic circuit of Fig.
2.4. The linear equivalent model is that of Fig. 4.1(c). The symbolic transistor in Fig.
4.1(b) is more intuitively representative in terms of the overall circuit perspective than that of Fig. 4.1(c). For this reason, the Fig. 4.1(b) version is chosen for use in all of the following discussions of MOSFET circuits. All other details of the transistor model, as discussed in this unit, will be added externally.
Signal Vg = Vi is applied to the gate (input) and, in response, a signal voltage, Vo, appears at the drain (or source). We would like to analyze the signal performance in terms of voltage gain, av = Vo/Vi = Vd/Vg (or av = Vs/Vg), of the circuit based on a linear (smallsignal) analysis. In any case, the voltage gain is av = GmRx, where Gm is the circuit transconductance (as opposed to the transistor transconductance) and x = D (common source) or x = S (source follower). Thus, the goal will be to obtain a relation for Gm for a given linear model of the transistor. Circuit transconductance is determined in the following for models with the various parameters included.

4.2. Transistor Variable Incremental Relationships
As illustrated previously diagrammatically, for example, in Fig. 3.2, the MOSFET is a four-terminal device. The four-terminal version of the schematic symbol is repeated here in Fig. 4.2. The terminals again are the source, drain, gate, and body. The drain current and the three terminal-pair voltages are all interdependent such that iD = f(vDS, vGS, vSB).
Use of the three-terminal schematic symbol for the transistor, as in Fig. 4.1, conveys the assumption that the body and source are connected. For an applied incremental Vgs, for example, there will be, in response, incremental drain current Id and incremental voltages
Vds and Vsb. The linear model is based on relating the current to the three voltages. This is
Equation 4.1

Figure 4.2. Four-terminal NMOS schematic symbol in a common source configuration. The linear-model representation is shown in Fig. 4.3. Figure 4.3(a) shows a currentsource version. The body-effect parameter, gmb, is defined as positive. The minus sign is required as the partial derivative in (4.1) is negative. In Fig. 4.3(b) the body-effect current source is reversed to eliminate the minus sign, and the current source associated with gds is replaced with a resistance. The latter is possible as the voltage-dependent current source is between the same nodes as the voltage.

Figure 4.3. (a) Linear model that includes all contributions to the signal drain current, Id, as given in (4.1). The body-effect parameter, gmb, is a positive number such that current from the current source is in the direction opposite the arrow. (b) Current source of body effect is reversed to eliminate the minus sign, and a resistor replaces the gds current source.

In the following units, using the detailed functions (3.8) and (3.14), which relate the four variables, expressions, as used in SPICE, will be obtained for the three proportionality constants: transconductance parameter, gm, output conductance parameter, gds, and bodyeffect transconductance parameter, gmb. The results will be used to obtain numerical results for the circuit transconductance, Gm, for various cases.

4.3. Transconductance Parameter
The transconductance parameter, gm, was introduced in Unit 2 in the treatment on the rudimentary electronic amplifier; it is the proportionality constant of the linear relationship between the output (responding) current and the input (control) voltage
[(2.3)]. For the MOSFET, NMOS, or PMOS, Id = gmVgs, where Id is into the drain for both transistor types. An ideal transistor can be modeled with this alone. A simple model, which includes no other components, would often be adequate for making estimates of circuit performance.
To obtain an expression for gm as a function of the general form iD = f(vGS, vDS, vSB) [e.g.,
(3.8)], we use the definition [from (4.1)]
Equation 4.2

Using (3.8) to express iD, the resulting relation for gm is
Equation 4.3

where
[(3.7)] and Veffn = VGS – Vtno. Note that the use of VDS is consistent with the partial derivative taken with respect to vGS, that is, Vds = 0. Also, the use of Vtno implies that vSB = 0. In general, VSB could be nonzero, although in the definition of gm, Vsb must be zero. For the case of nonzero VSB (bias), one substitutes for
Vtno a constant Vtn(VSB) in the gm expression.
Alternative forms for the gm expression can be obtained from (3.8), which is, solving for
Veffn,
Equation 4.4

Using (3.8), (4.3), and (4.4), gm takes on altogether three forms:
Equation 4.5

Usually, in initial design, kn replaces serious penalty in accuracy.

to eliminate the VDS dependence without a

Using the simple linear transistor model, an expression for the circuit transconductance,
Gm, for the circuit of Fig. 4.1 will now be obtained. The input loop equation for an applied gate signal voltage, Vg, is
Equation 4.6

which is, with Vgs = Id/gm,
Equation 4.7

and
Equation 4.8

The far right-hand side uses (4.5). For example, for a 1-V drop across RS and Veffn = 0.5
V, Gm = gm/5. Note that the ratio of the signal voltage drop across RS and signal voltage
Vgs is gmRS:1. The Gm concept is utilized routinely in MOSFET circuits (and BJT circuits), which gives the effective reduced transconductance, referred to Vg, in the presence of the source resistor.

4.4. Body-Effect Transconductance Parameter
For circuits in which the signal Vsb is nonzero, there will be an additional component of
Id, gmbVsb. An example is the circuit of Fig. 4.1 but with body terminal connected to ground. This feature is added to the circuit as shown in Fig. 4.4. The proportionality constant for this case, gmb, is the body-effect transconductance. It is defined as
Equation 4.9

Figure 4.4. Signal circuit with the addition of a current source due to the body effect. In this example, Vb = 0 V and Vsb = IdRS.

which is [with (3.8) and (3.14) for iD and Vtn]
Equation 4.10

The minus sign is consistent with a current source in the opposite direction from that of
Fig. 4.4 (as shown in Fig. 4.3) as iD is defined as positive into the drain. The preference is to turn the current source around as in Figs. 4.3 and 4.4 and use positive gmb. The result for gmb is a factor, η, times gm, that is
Equation 4.11

For γn = 0.5 V1/2, VSB = 5 V, and 2ΦF = 0.7 V, gmb = 0.1gm (η = 0.1). Note that gmb is not zero even with the source connected to the body [i.e., with VSB = 0 in (4.11)]. However, signal Vsb is zero in such a case, such that gmb does not have to be taken into account. In general, even with VSB 0 it is possible for Vsb 0, in which case, gmb must be included

in the model (e.g., in Project 8 on the study of the source-follower stage, at the low end of the bias current scan).

4.5. Output Conductance Parameter
The output conductance accounts for the finite slope of the output characteristic, an example of which is shown in Fig. 4.5. The plot for the SPICE formulation [(3.8)] of the active region is also shown (applicable to the device for VDS > Veffn). Both plots are for
VGS = constant (i.e., Vgs = 0 and gmVgs = 0).

Figure 4.5. Output characteristics illustrating nonzero active-region slope. Also shown is the SPICE formulation for the active region. For the plots, λn = 1/10 V.
A possible bias point with ID and VDS is included.

In the ideal case, for any vDS in the active region, the current is the same for a given VGS, and the drain current is simply Id = gmVgs. The real case, though, obviously possesses a current dependence on vDS. The linear model treats gm as a constant (calculated at the bias values) and includes the effect of the nonzero slope with the output conductance, gds, such that Id = gmVgs + gdsVds (without or neglecting the body effect). The circuit shown in
Fig. 4.6 includes the gds component.

Figure 4.6. Signal circuit that includes addition of the output conductance. The equivalent resistance has magnitude 1/gds.

An expression for the output conductance is obtained from the definition
Equation 4.12

Again using (3.8), the result is
Equation 4.13

where Veffn = VGS – Vtno is constant and where ID is the dc (bias) current. The last term
(on the right-hand side) is the form that is generally used in practice for an initial design, as it does not require a value for VDS. Note that gds is not a conductance in the physical sense but has the correct dimensions and behaves in the circuit like a conductance.
We will now obtain the circuit transconductance for the case where the effect of gds is included. Upon application of an input signal, Vg, a signal drain current, Id, will flow in the output circuit. This causes a signal voltage to appear across RS and RD, which is equal to the voltage to Vds. That is,
Equation 4.14

The associated current through the output resistance is thus
Equation 4.15

The effect is to reduce the current through RS and RD and thus reduce the circuit transconductance of the common-source amplifier stage. The output current with the current of (4.15) subtracted from the basic gmVgs is
Equation 4.16

which is, when solved for Vgs,
Equation 4.17

Again using (4.6), which is Vg = Vgs + IdRS, the new circuit transconductance is
Equation 4.18

With a 1 - V drop across RS and a 5 - V drop across RD, and with λn = 1/50 V, the new
Gm is gm/5.12, compared with gm/5 when neglecting gds [(4.8)].

In general, the complete circuit includes, in addition, the body-effect transconductance current source of Figs. 4.3 and 4.4. The omission of this current source in Fig. 4.6 implies that Vsb = 0 because the source and body are connected. This connection is possible to implement in special cases such as in some of our MOSFET lab projects where only one transistor on the chip is used or for the case of a differential stage where the source of two transistors is at the same node. It is also possible to eliminate the body-effect current source by bypassing the source resistor with a bypass capacitor. The capacitor places the source at signal ground. However, in this case, the dc threshold voltage is still affected by
VSB = IDRS.
In Unit 8, the circuit transconductance equivalent to (4.8) and (4.18), but which includes the body effect [(8.49)], is given as

where η is defined in (4.11). For gds = 0 and η = 0, (4.19) reduces to (4.8). Note that including the body effect will in general have more effect on Gm than including gds, as η can be on the order of 0.2. In all cases where we can calculate the circuit transconductance, Gm, the magnitude of the voltage gain is obtainable from –GmRD
(common-source stage) and GmRS(source-follower stage).

4.6. Graphical Perspective of Output Characteristics and the Load
Line
The transistor output characteristics from Unit 3 and the variable increments along with their linear relationships are illustrated in Fig. 4.7. This would be applicable, for example, to the amplifier of Fig. 2.4. (As in that circuit, no body effect is included.) The circuit is biased with drain – source voltage VDS and drain current ID. A positive signal Vg is applied to the gate terminal. In response, there appears drain signal voltage –Vd, due to the rise in drain current. Signal voltages are with respect to the source or ground.

Figure 4.7. Transistor output characteristics without and with input signal, Vg.
A solution for the drain current and drain – source voltage in both cases is the intersection between the respective characteristics and the load line of the amplifier circuit.

The two output characteristic curves correspond to bias VGS only and with gate voltage
VGS + Vg. In both cases, the solution to the drain current and voltage is the intersection between the transistor characteristic curve and the load line, which is a plot of the output circuit loop equation. This is (with reference, for example, to Fig. 2.4)
Equation 4.19

The solution is always constrained to this straight-line equation. The solution for vDS with and without signal is based on (4.19) and (3.8), which is

The combined contributions to Id associated with the two g parameters is
Equation 4.20

By the nature of the load-line function, the two terms will always have opposite signs; when Vg is negative, Vd will be positive.

4.7. Summary of Equations
Transconductance.

where

Approximate transconductance.

where

Amplifier circuit transconductance with a source resistance. Body-effect transconductance.
Output conductance. gds = λnID

Approximate output conductance.
Amplifier circuit transconductance with gds included. Subscripts are for NMOS. All equations are the same for PMOS with "p" subscript substitution and subscript-order reversal for bias-voltage variables.

Unit 5. Common-Source Amplifier Stage
Two types of common-source amplifiers will be investigated in lab projects. One is with the source grounded and the other is with a current-source bias (dual power supply). In
Units 5.1 and 5.2 we discuss various aspects of the common-source stage with grounded source, in Unit 5.3 we take up circuit-linearity considerations, and in Unit 5.4 we cover the basics of the dual-power-supply amplifier. Both amplifiers are based on the PMOS, as in the projects. The first two units are mostly a review of the basic amplifier as presented in previous units, to reinforce the basic concepts. The PMOS replaces the NMOS (Units 2 and 4) in this unit, to provide familiarity with the opposite polarity in bias considerations and to illustrate that the linear model applies in the same manner for both transistor types.

5.1. DC (Bias) Circuit
Dc circuits for the grounded-source amplifier are shown in Fig. 5.1 (PMOS). The circuit in (a) is based on a single power supply, and the gate bias is obtained with a resistor voltage-divider network. The circuit in (b) is for a laboratory project amplifier. Both VGG and VSS are negative, since the source is at ground. There is no voltage drop across RG since there is negligible gate current. RG is necessary only to prevent shorting the input signal, Vi. The bias current ID for a given applied VSG will respond according to (3.8), which is
ID = kp (VSG – Vtpo)2(1 + λpVSD)

Figure 5.1. Basic PMOS common-source amplifiers. Single-power-supply amplifier (a) and laboratory amplifier (b) with VSG (= VGG) and VSS controlled by
DAQ output channels. Note that either end of the circuit of (a) can be at ground.

The two circuits are equivalent, as VGG and RG of Fig. 5.1b are the Thévenin equivalent of the bias network of the Fig. 5.1(a). In the project on the amplifier, they are actually a voltage and a resistor. This is not a bias-stable circuit, as a slight change in VSG or the transistor parameters can result in a significant change in ID. The dual-power-supply circuit of Unit 5.4 is considerably better in this respect.

5.2. Amplifier Voltage Gain
This dc (bias) circuit becomes an amplifier now simply by adding a signal source at the gate as in Fig. 5.2. This requires a coupling capacitor, as shown here in the complete circuit, to prevent disturbing the bias upon connecting the input signal to the circuit.

Figure 5.2. A signal source is connected to the gate through a coupling capacitor. The capacitor is necessary to isolate the dc circuit from the signal source. In the amplifier of Project 5, the signal will be superimposed on the bias voltage at the node of VGG. This can be facilitated with LabVIEW and the DAQ. A capacitor, as in an actual amplifier, is therefore not required. The requirement for having LabVIEW control over both VGG and VSS, and the limitation of two output channels, dictates this configuration. In Project 5 we measure the gain as a function of bias current, ID. For a SPICE comparison, we need an expression for the gain. For the ideal case, which neglects the output conductance, gds, the output current is related to the input voltage by (4.1), which is Id = gmVgs = gmVi
The output signal voltage is, in general,
Equation 5.1

The convention used here for subscript order for signal (linear) variables is common to the NMOS and PMOS. This is consistent with the fact that the linear model does not distinguish between the two types. Thus, for example, the dc terminal voltage for a
PMOS is VSG, but the signal equivalent is Vgs (Fig. 5.3) and the signal input voltage is positive at the input terminal (common-source, gate input). For the PMOS, iD is defined as positive out of the drain, but the signal output current is into the drain (as in the
NMOS). We note that a positive Vgs (Vgs = –Vsg) corresponds to a decrease in the total gate – source voltage, vSG, which is consistent with a decrease of iD and positive Id.

Figure 5.3. Signal-equivalent version of the amplifier stage. Dc nodes are set to zero volts (circuit reference). The reactance of Cg is assumed to be zero.

Thus, the negative sign in (5.1) is consistent with the flow of current Id up through the resistor (Fig. 5.3) for positive Vi = Vgs. The common-source stage is an inverting amplifier and has an inherent 180° phase shift. From (4.1) and (5.1), the gain is
Equation 5.2

where both Vi = Vgs and Vo = Vds are with respect to ground or the source terminal for the common-source stage.
If the output resistance, 1/gds, cannot be neglected (which is the case for the project on
PMOS amplifiers), the transistor current, gmVi, is shared between the output resistance and RD. The portion that flows through RD is (Fig. 5.4)
Equation 5.3

Figure 5.4. Common-source amplifier stage signal circuit, with all dc nodes set to zero volts. The transistor model includes output resistance 1/gds, which appears directly in parallel with RD with the source grounded.

Note again that the signal schematic transistor represents a current source with value gmVi, as established in connection with Fig. 4.1. The additional feature of the transistor model is included with the addition of 1/gds. This resistance is actually part of the transistor and is between the drain and source of the transistor, but the circuit as given is equivalent, as the source is at ground. Since the output voltage is Vo = –IRDRD, the new gain result is
Equation 5.4

Note that this form evolves from ideal transistor current, gmVgs, flowing through the parallel combination of the output resistance and RD.
To facilitate an intuitive grasp of the magnitude of the effect of gds, we use the expression for gds (4.13) in (5.4), to obtain
Equation 5.5

Note that IDRD is the voltage drop across RD. For example, for a –10-V power supply, we choose IDRD 5 V. A measurement of λp for our devices will show that λp 1/20 V, which results in λpIDRD 1/4. Thus, the effect of gds (= λpID) for this case is significant.
Finally, we can get an overall current dependence for av with the elimination of gm, using(4.5) with kp, which results in

Equation 5.6

Using an alternative form for gm (= 2ID/Veffp), also (4.5), the gain expression is
Equation 5.7

where

For simplicity, approximate forms of (4.5) and (4.13) of gm and gds are used here, which are independent of VSD. For reference, the "exact" and approximate forms of (4.5) and
(4.13), respectively, are repeated here:

and

The "exact" equations of gm and gds are used in conjunction with the amplifier projects to compare the computed gain with the measured gain plotted against ID. This is done in both LabVIEW and Mathcad. Parameters kp and Vtpo (to get Veffp) will be extracted from the measured dc data, and λp will be used as an adjustable parameter to fit the SPICE and measured gain data.

5.3. Linearity of the Gain of the Common-Source Amplifier
The connection between Id and Vgs is linear provided that Vgs is small enough, as considered in the following units. Use of the linear relations also assumes that the output signal remains in the active region (i.e., neither in the linear region nor near cutoff). This is discussed below. NMOS subscripts are used. The results are the same for the PMOS, with a "p" subscript substituted for "n" and the subscript order reversed for all biasvoltage variables.

5.3.1. Nonlinearity Referred to the Input
The general equation again is (3.8)

Then using Id = iD – ID and vGS = VGS + Vgs, the equation for the incremental drain current becomes Equation 5.8

which leads to a nonlinear (variable) transconductance,

, given by

Equation 5.9

Therefore, the condition for linearity is that Vgs > 1. This is typically only marginally satisfied in MOSFET circuits.
The derivation carried out here was initiated from (5.15), which neglects the output resistance of the transistor. In the case of the MOSFET devices of our projects, the simplification is valid for the NMOS transistor but marginal for the PMOS transistor.
This is because λp >> λn. The result (6.9) still serves to estimate the required value for Cs, even for the case of the PMOS. Nevertheless, a more detailed derivation is carried out in the next unit. This permits comparisons, in a project, of SPICE and Mathcad solutions with amplifier gains and frequency response.

6.3. Precision Formulation of the Low-Frequency Gain and
Characteristic Frequencies
In Unit 8, the gain of a common-source stage with source resistor, which includes the effect of the output resistance, is shown to be [(8.36)]

This is designated here as avolo to emphasize that it is the constant low-frequency asymptotic gain. If the source-branch impedance is substituted for RS, this becomes
Equation 6.10

where fz is (6.5). This can be rearranged in the form of (6.4), which is
Equation 6.11

where the new pole frequency is
Equation 6.12

and avolo is (8.36).

6.4. Load Coupling Capacitor
The complete practical amplifier includes a load, RL, at the output. This requires an additional coupling capacitor. The amplifier with an attached load is shown in Fig. 6.3.
We will assume that the effect of the output resistance, rds, can be neglected. The transistor appears as a current source of magnitude Id. The equivalent signal circuit at the output can be represented as shown in Fig. 6.4(a) and (b). In Figure 6.4(b), the current source and drain resistor are replaced with a voltage-source equivalent. From Fig. 6.4(b), the output voltage is
Equation 6.13

Figure 6.3. Amplifier with capacitively coupled load resistor, RL. The capacitor must be large enough not to attenuate the output between the drain and load resistor. The expression with the high-frequency asymptotic value and frequency dependence is
Equation 6.14

which is
Equation 6.15

where
Equation 6.16

Figure 6.4. (a) Equivalent circuit consisting of a current source and the load components. (b) Conversion of current source to voltage source.

Current source Id is not dependent on frequency (at the low end of the spectrum) when no other capacitors are considered. However, in general, with both Cd and Cs attached, the combined response is
Equation 6.17

where fd is (6.16), fz is (6.5), fs is (6.6), and is RD in parallel with RL. With Cd = Cs, usually fd ½. Note that for both inverting and noninverting gains, the effect of Rbias can be neglected for most purposes, as the multiplying fractions in (8.19) and (8.20) are both close to ½.
The choice of the input at gate 1 is arbitrary and all of the results obtained here apply equally to the input taken at gate 2. The inverting output is always at the side of the input, and the noninverting output is always at the opposite side.

8.5. Differential Voltage Gain
Suppose that an input voltage, Vg12 = Vg1 – Vg2, is applied between the inputs. Due to symmetry, the voltage magnitudes at the inputs with respect to ground are Vg1 = Vg12/2 and Vg2 = –Vg12/2, respectively. The noninverting output, Vd2, for this case is, by superposition, Equation 8.21

The gains for the contributions from Vg1 and Vg2 are (8.19) and (8.20), respectively. This is the case of a pure differential input with resulting gain
Equation 8.22

A similar approach applied to obtain the gain for the output taken as Vd1 produces
Equation 8.23

Assume, for a numerical example, that ID = 100 μA, RD1 = 50 KΩ, and gm = 200 μA/V
(Veffn = 0.5 V). In this case the gain is avd1 = –10. This would be consistent with VDD =
|VSS| = 10 V.
The gain for the case of the differential output, avd12 = (Vd1 – Vd2)/(Vg1 – Vg2), can be obtained from (Vd1 – Vd2) = –(1/2)gm1RD1Vg12 – (1/2)gm2RD2Vg12 and is
Equation 8.24

where gm1 = gm2 and RD1 = RD2 = RD. Note that (8.22) and (8.23) are the same as (8.15) and (8.17). However, (8.15) and (8.17) are the limiting forms of (8.19) and (8.20) for
Rbias
, whereas (8.22) and (8.24) apply for a finite Rbias.

8.6. Common-Mode Voltage Gain
The common-mode gain is defined for the same voltage applied simultaneously to both inputs. The output must be the same at either output terminal (again assuming that gm1 = gm2 and RD1 = RD2). For example, for the output Vd2, the gain can be determined by a superposition of gains, inverting (input, Vg2) and noninverting (input, Vg1), with RD2 in both equations.
Using (8.19) (noninverting) and (8.20) (inverting), the gain for finite Rbias is, accordingly,

Equation 8.25

which is
Equation 8.26

The result is that of a common-source stage with source resistance 2Rbias. This is intuitively correct as taken from the half-circuit viewpoint, where the circuit is completely symmetrical. The input from either side looks at a common-source stage except that the opposite side is contributing an equal amount of source current, thus giving an effective source resistance equal to twice the actual value. A valid approximate form for well-designed circuits (in terms of common-mode gain) is
Equation 8.27

The same result applies to the case of the output taken at the opposite drain, with the substitution of RD1 for RD2. Using the circuit values following (8.23) plus Rbias = 85 kΩ, avcm –0.3. Note that this result in combination with the gain from (8.23) would indicate that this is not a particularly good design. The goal is for avd >> avcm.

8.7. Voltage Gains Including Transistor Output Resistance
In Project 9 we measure the gain of a "balanced" stage with drain resistors for both transistors. The amplifier is the PMOS version of the NMOS amplifier of Fig. 8.2. We obtain an exact Level 1 SPICE solution for the gains for both outputs. The example is used to explore the use of a simulator for obtaining precision results to compare with simple hand calculations.
For larger λn values (NMOS), the output resistance can influence the gain and complicate the gain expressions considerably. Here we consider the effect due to gds1 and gds2 while

retaining the effect of Rbias. In the following, the gain of the inverting input, av1, is obtained again as a common-source stage with source resistance. The effect of gds2 on the effective source resistance is included (input at the source of M2). The effects due to gds1 are also taken into consideration.
The gain of the noninverting case, av2, is obtained by considering the cascade of the source follower stage (M1) and the common-gate stage (M2), as, in effect, was done in the development of (8.19). The source-follower gain takes into account effects from gds1 and gds2, and the gain of the common-gate stage depends on gds2.

8.7.1. Gain of the Common-Source Stage with Transistor Output
Conductance and Source Resistor
The circuit transconductance for a common-source stage with source resistor, with the inclusion of gds, was developed in Unit 4 [(4.18)]. This will be reviewed and reinforced here in the form of a slightly different approach to the result. The signal circuit for this case is again given in Fig. 8.4. Using the variables of Fig. 8.4, the circuit transconductance is Gm1 = Id1/Vi. The object is thus to obtain a relation between these two variables. Figure 8.4. Circuit for obtaining the gain for the inverting output with the transistor output resistance included. Rs includes all resistance contributions at the source.

The fraction of the current produced by the intrinsic transistor, gm1Vgs1, which flows into
Rs is
Equation 8.28

This is the portion of current source gm1Vgs1, shared between 1/gds and RD + Rs, which flows through RD + Rs, that is, Id1. Note that RD + Rs and 1/gds1 are in parallel and shunt the transistor current source.
A relation for Vgs1 in terms of Id1 follows, which is
Equation 8.29

The input Voltage is the sum of Vgs1 and the drop across Rs. That is,
Equation 8.30

Using (8.29) in (8.30) gives
Equation 8.31

or
Equation 8.32

The circuit transconductance follows as
Equation 8.33

The gain for this case is then
Equation 8.34

A discussion of Rs as affected by gds2 follows.

8.7.2. Common-Gate Amplifier Stage
The circuit diagram of Fig. 8.5 is for the M2 portion of the differential amplifier. The input is applied at the source, Vs2, and the output is taken at the drain, Vd2 = Vo2, while the gate is grounded. This is a common-gate configuration. Here we analyze the input resistance, for evaluating the effect on Rs, and gain of the common-gate stage.

Figure 8.5. Circuit that includes the output resistance of M2. The circuit is for obtaining input resistance at the source of M2 and the gain of the common-gate stage of M2

Without gds2, the input resistance at the source is just 1/gm2. With gds2 in place, there is a positive feedback from the drain output to the source input. This causes the input resistance to increase. With gds2, the current into the source terminal is

Equation 8.35

It is noted that the gds2 term reduces the input current, which has the effect of increasing the input resistance. From (8.35), the resulting input resistance at the source, Ris2 = Vs2/Id2, is Equation 8.36

The input resistance goes to 1/gm2, as noted above, for gds2 = 0. The expression for the equivalent Rs is now Rs = Rbias || Ris2, where Ris2 is (8.36). In modern integrated circuits,
RD2 may be replaced with a high-resistance transistor current source, and the input resistance is this case can be much greater than 1/gm2.
The gain of the common-gate stage is obtained as follows: The output voltage is
Equation 8.37

which gives
Equation 8.38

Note that for gds2 = 0, the gain has the same magnitude as the simple case for the common-source stage.

8.7.3. Voltage Gain for the Noninverting Output
The noninverting amplifier gain is based on a cascade of a source-follower stage (M1) and a common-gate stage (M2). The source-follower transconductance, Id1/Vi, is (8.33).
Using this with Vs1 = Id1Rs gives
Equation 8.39

Note that the magnitude is about ½. Overall gain is the product of (8.38) and (8.39), which is
Equation 8.40

The equations from this unit are summarized below in Unit 8.11.
Recall from the discussion of MOSFET model parameters that gds is given by (4.13), which is

Thus, the gain expression depends on parameter λ, and especially if λ is somewhat large.
In Project 9 we measure the gains from the two drains and use the results to find the value of λ that makes the theory fit the measurements. In this way, we are getting a signalderived experimental number to compare with that obtained in the parameterdetermination project. This will be done using the PMOS configuration since the value of λp is large and the effect is significant. All of the gain expressions, which are based on
NMOS transistors, apply exactly to the PMOS stage with substitution of subscripts; change n to p (parameters) and reverse the order for dc voltage variables.
For hand calculations, approximate forms must reasonably be used. This applies to approximate forms for device parameters and gain. The basic gain equations are, again, assuming that gds = 0 and Rbias = , simply, as given by (8.15) and (8.17),

with RD1 = RD2 and gm1 = gm2. In the differential amplifier project, we will compare these with the more precision forms.

8.8. Body Effect and Voltage Gain
In Project 9 we are able to connect the sources of the transistors to the chip body.
Certainly, in general this cannot be done such that there is a body effect associated with the differential-amplifier-stage transistors. The necessary alterations to the gain equations are determined in the following. At the end of this unit, we will have the complete, precision-gain calculation equations of Level 1 SPICE. It will be informative to consider numerical results that are based on various degrees of approximations, and this is done below. 8.8.1. Common-Source Stage and Body Effect
With the body effect present, a component of current, gmb1Vs (Fig. 8.6), is subtracted from gm1Vgs1 such that (8.28) for this case is modified to become
Equation 8.41

Figure 8.6. Circuit for obtaining the inverting gain of the differential stage with body effect included. Body effect is accounted for by the current source added to the transistor signal (linear) equivalent circuit.

Additionally using Vs = Id1Rs and Vgs1 = Vi – Id1Rs (8.30)] in (8.41), a relation between Id1 and Vi is obtained, which is
Equation 8.42

Solving for Id1, the circuit transconductance is, for the body-effect case,
Equation 8.43

It follows that the gain for the inverting mode, with the addition of body effect, is
Equation 8.44

The effect of ηn in the denominator tends to make the gain smaller. However, the body effect, as shown below, will decrease Rs such that the two effects tend to cancel one another. 8.8.2. Common-Gate Stage and Body Effect
The voltage applied to the common-gate stage is Vs2 = Vsg2 (Fig. 8.7). Recall that in the g model for the transistor, as discussed for the common-source mode, current sources gmbVsb and gmVgs are in parallel but in opposite directions. Thus, the current sources gmVsg and gmbVsb are, for the common-gate mode, in the same direction since Vsb = Vsg =
–Vgs; the common-gate has an effect transconductance of (1 + η)gm. It follows that the input resistance of the common-gate stage is as obtained before the body effect was included [(8.38)], except for the addition of ηn, as in the following:
Equation 8.45

Figure 8.7. Circuit that includes the voltage-dependent current source due to body effect associated with M2. Body effect affects the input resistance into the source of M2 and the gain of the common-gate stage of M2.

Similarly, the common-gate gain, (8.38), is readily modified with the addition of the multiplying factor (1 + ηn). This is
Equation 8.46

Note that in the absence of gds2, the gain for the common-source stage reduces to avcd = gm2 (1 + ηn)RD2, where, with body effect, the effective transconductance is, again, (1 + ηn) gm2. 8.8.3. Source-Follower Stage with Body Effect
The transconductance relation obtained for the common-source stage given by (8.43) also applies to the source-follower stage. Combining this with Vs1 = Id1Rs leads to the sourcefollower gain associated with M1, which is
Equation 8.47

The overall gain is again av2 = avsf avcg
Note that the body effect for the source-follower stage increases the denominator of (8.49) while it increases the numerator in the common-gate result, (8.48). These tend to cancel, as in the case of the inverting gain.

8.9. Amplifier Gain with Differential and Common-Mode Inputs
For inputs at either or both gates, there exists a common-mode and differential-mode voltage. These are, for applied voltages Vg1 and Vg2, common mode
Equation 8.48

and differential mode
Equation 8.49

Based on these definitions, the output, for example, Vd1, for a given set of inputs is
Equation 8.50

where avd1 and avcm are (8.23) and (8.26) (with RD1), respectively. For the output Vd2, avd2 is substituted for avd1. Vdm is a pure differential input and is not with respect to ground; the effect from the bias resistor is accounted for in the common-mode gain.
For the case of a single-ended input, for example, Vg1 = Vi and Vg2 = 0, the output is
Equation 8.51

This is identical to (8.20). The common-mode contribution can be significant, for example, in a resistance feedback amplifier (Unit 11). In this case, Vdm in (8.50) can be very small compared to Vcm.

8.10. Comparison of Numerical Gain Results
Gain calculations were made using kn = 1000 μA/V2, λn = 0.05 V–1, RD = 150 kΩ, Rbias =
100kΩ, ηn = 0.15, ID = 50 μA, and VDS = 5 V. The values are given in Table 8.1. For the comparison, gm was calculated with the precision form [(4.5)] (λn 0) for all cases.
Possibly a more valid consistency (hand calculation versus precision calculation) would be achieved with the use of the approximate form for gm up to λn 0. This would reduce some of the difference in the results. For example, for the first case, av1 = –av2 = –33.5, with the approximate form for gm (λn 0).
TABLE 8.1
Gain Magnitudes
Rbias =

, λn = 0, ηn = 0

plus Rbias = 100KΩ

av1

av2

37.5

37.5

37.9

37.1

TABLE 8.1
Gain Magnitudes

av1

av2

plus λn = 0.05V–1

29.21

28.48

plus ηn = 0.15

29.17

28.53

It is notable that the various factors do not have a major effect on the results, even though the value of λn is relatively large. This is especially true for the differential amplifier with resistive load, as considered here. The conclusion can be made that for initial handcalculation purposes, the simplest form is satisfactory. Precision results can be obtained with a simulator.

8.11. Summary of Equations
Differential-stage bias equation.

Threshold voltage for with VB = VSS and thus VSB = 2IDRbias.
Approximate relation for drain-current imbalance due to kn1 kn2 and Vtno1
Vtno2.
,

Ideal voltage gain, Rbias
0, gm1 = gm2 = gm.

and gds =

Gain Vd2/Vg1 = Vo2/Vi for noninverting output with finite Rbias.
Gain Vd1/Vg1 = Vo1/Vi for inverting output with finite Rbias.
Gain Vd1/Vg1 = Vo1/Vi for inverting output for source resistance, Rs, with gds 0.
Rs = Ris2 || Rbias
Input at the source of M2 with gds
0.

Differential-stage bias equation.

Gain Vd2/Vs2 = Vo2/Vs2 for commongate stage of M2 for gds 0.
Gain Vs1/Vg1 = Vs1/Vi of sourcefollower with input at gate of M1 and output at source of M1.
Gain Vd2/Vg1 = Vo2/Vi for noninverting output and gds 0. avd12 = –gmRD

Gain for differential input, differential output with RD1 = RD2 and gm1 = gm2.
Common-mode gain.

Inverting-input gain Vd1/Vg1 = Vo1/Vi, including body effect.
Rs = Ris2 || Rbias
Input at the source of M2, including body effect and gds 0.
Common-gate gain Vd2/Vs2 = Vo2/Vs2 of M2, including body effect.
Source-follower gain Vs1/Vg1 = Vs1/Vi of M1, including body effect. av2 = avsfavcg

Gain Vd2/Vg1 = Vo2/Vi, including body effect, gds 0.

8.12. Exercises and Projects
Project Mathcad Files Exercise09.mcd - Project09.mcd
Laboratory Project 9

MOSFET Differential Amplifier Stage

P9.2

DC Evaluation of the Single-Power-Supply Differential Amplifier

P9.3

Determination of the PMOS Parameters

P9.4

Amplifier Gain Measurement

P9.5

Transistor Parameters and DC Imbalance

Project Mathcad Files Exercise09.mcd - Project09.mcd
P9.6

Common-Mode Gain Measurement

Unit 9. MOSFET Current Sources
With the evolution of integrated circuits, it was necessary to reduce the number of resistors in the circuit, and the solution was the transistor current source. An added bonus was that the circuit was generally greatly improved as well. Here, the basic principle is introduced, followed by a discussion of the standard method of increasing the current output resistance with source degeneration. The application of a current-source configuration for balancing a differential amplifier stage is discussed.

9.1. Basic Current Source
An example of a current source based on PMOS transistors is shown here in Fig. 9.1. It consists of the reference circuit, consisting of transistor M3 and bias resistor Rbias. The reference-circuit transistor is diode connected. The induced VSG3 = VSD3 is applied to the current-source transistor M2. Thus, the drain current, or current-source current of M2 is the mirror of the reference current. In an integrated circuit, any number of current sources can be referenced to the reference current or voltage. Current ratios are implemented with the selection of the relative gate widths of the transistors.

Figure 9.1. PMOS current source. The current set up by the reference circuit of
M3 and Rbias is mirrored as the current of M2.

The design of the reference circuit is based on a dc solution to the reference current, ID3.
The solution is obtained from the loop equation
Equation 9.1

and transistor equation
Equation 9.2

The current in M2 is
Equation 9.3

where

and

W2 and W3 are the transistor gate widths of M2 and M3, respectively, and L is the channel length. In general, the ratio of currents is
Equation 9.4

where the approximation can often be used for simplicity with long-channel devices. This avoids the necessity of knowing the source – drain voltages. The signal output resistance at the drain of M2 is
Equation 9.5

In the project of the current source, we will scan VSD2 and compare the source current with the reference current.

9.2. Current Source with Source Degeneration
It is normally desirable to have the output resistance of a current source as large as possible. It can be improved over the circuit of Fig. 9.1 by adding resistance in the source branch, as shown in Fig. 9.2, to establish source degeneration (negative feedback). In the discussion of the signal circuit, it is necessary to represent the diode-connected transistor with its linear equivalent, which is just a resistance of magnitude, 1/gm. This can be seen by inspection of the circuit of Fig. 9.3. The voltage, Vd, is applied directly to the gate such that Vgs = Vd and the drain current is Id = gmVd. Thus the resistance of the diode is just Vd/Id = 1/gm. The result is the same for the PMOS and NMOS as is always true for signal linear models.

Figure 9.2. Current-source circuit with source resistors to improve output resistance at drain of current-source transistor, M2.

Figure 9.3. Signal circuit for diode-connected NMOS.

The new output resistance at the drain of M2 for the current-source circuit with source resistors (Fig. 9.2) can be derived based on the signal circuits shown in Fig. 9.4. The output resistance is defined as Ro = Vo/Io, where Io is the drain current flowing in conjunction with the application of the test voltage Vo. Figure 9.4(b) replaces M3 with the signal model equivalent and M2 with the ideal, intrinsic transistor model (current source) along with output resistance,1/gds2. The transistor symbol represents the ideal transistor with output current gm2Vsg2, positive in the direction shown.

Figure 9.4. (a) Signal circuit of Fig. 9.2. (b) Reference transistor circuit replaced with the linear model. The effective resistance at the gate of the current source transistor plays no role other than to return the gate to ground since Ig2 =
0.

The current Io flowing through the transistor and up through the resistor, RS2, develops a voltage across the resistor, VRS2 = IoRS2. Since Ig2 = 0, an input circuit loop equation is simply Vgs2 = –IdRS2. The transistor linear-model current source, gm2Vgs2, thus is down, as shown in the signal-circuit diagram of Fig. 9.4(b). The sum of currents through 1/gds is
Equation 9.6

The voltage Vo is thus
Equation 9.7

and the output resistance is
Equation 9.8

This magnitude can be assessed with the use of (4.5), which is gm = 2ID/ Veffp.
Eliminating gm in (9.8) results in
Equation 9.9

If the magnitude of the voltage across RS2 is several volts, then Ro is much greater than
1/gds2, since Veff2 is typically a fraction of a volt. In integrated circuits, RS may be replaced with an additional current source, in which case the expression becomes
Equation 9.10

where the output resistance of the added current source is approximately 1/ID2λp [(4.13)].

9.3. Differential Amplifier Balancing Circuit
The principle of the balancing of the differential-amplifier stage (e.g., in an opamp) is often based on a circuit similar to that in Fig. 9.2, as shown in Fig. 9.5. Imbalance could be due, for example, to Vtpo1 Vtpo2 and kp1 kp2. Balancing is implemented by adjusting R1 R2, where R1 = RS1//Rx and R2 = RS2||Ry.

Figure 9.5. Balancing circuit. Voltage VD2 is controlled by selecting the relative values of Rx and Ry.

The relationship among the currents, parameters, and resistors is obtained by writing the loop equation around the source resistors and the gate – source terminals, which is
Equation 9.11

A solution for VSD2 can be obtained from (9.11) for a given set of parameters, resistors, and bias variables; on the other hand, Rx and Ry are adjusted to obtain a certain VSD2.
For the special case of ID1 = ID2 = ID, the difference between the resistors in (9.11) is
Equation 9.12

For a numerical example, suppose the goal is to set design, in (9.12),
Equation 9.13

. By

Any slight possible difference in λp is neglected.
In a practical opamp with this balancing configuration, the source nodes are connected to external pins. These pins are connected through external resistors Rx and Ry to VDD as shown in Fig. 9.5. For adequate adjustment sensitivity, Rx and Ry are greater than RS1
RS2 by at least a factor of 10. In practice, the external resistances are implemented with a potentiometer. Assume that the transistor parameter values are Vtpo1 = 1.49 V, Vtpo2 = 1.51 V, kp1 = 345 μA/V2, kp2 = 335 μA/V2, and λp = 0.02 V–1. Also assume that the bias current ID = 100 μA. We select RS1 = RS2 = RS = 3 kΩ (Voltage IDRs = 0.3 V) and we use Rx + Ry = Rpot =
25 kΩ; the two resistors are segments of a 25-kΩ potentiometer. The segments of the potentiometer are then determined from a solution to
Equation 9.14

where δR is obtained from (9.12) with VSD2 = VSG1 as obtained from (9.13). The resistor values are Rx = 16 kΩ and Ry = 9 kΩ to give R1 = 2.53 kΩ and R2 = 2.25 kΩ.
An evaluation of VSD2 without the balancing circuit can be made by setting δR = 0 in
(9.12) and for solving VSD2 to obtain
Equation 9.15

VSG1 is again obtained from (9.13).

With the numbers from the example above, VSD2 = 7.87 V. We note that with λp = 0.01
V–1, the solution is VSD2 = 13.2 V and the circuit might well have exceeded the powersupply limits. If Vtpo1 = 1.45 V, Vtpo2 = 1.55 V, and λp = 0.02 V–1 that is, for an extreme case of the difference of threshold voltage, the balancing circuit will still function but now Rx = 21.8 kΩ and Ry = 3.24 kΩ with a small R2 = 1.56 kΩ.

9.4. Summary of Equations
Reference current, ID3, and currentsource current, ID2, relation.
Output resistance of current-source with source degeneration.
Output resistance of current-source with source degeneration and gm =
2ID/Veffp.
Relation for setting VD2 in balancing circuit with R1 = RS1//Rx and R2 =
RS2 ||Ry. δR = R1 – R2
Relation for VD2 = VD1 for ID1
ID2 = ID.
VSD2 for unbalanced circuit with δR
= 0 and ID1 = ID2 = ID.

Unit 10. Common-Source Amplifier with CurrentSource Load
The amplifier in this part is the same, in principle, as the basic common-source amplifiers of Figs. 2.4 and 5.1. However, now the actual resistor RD is replaced with a currentsource load as shown in the circuit of Fig. 10.1. As noted in Unit 9, a benefit of replacing bias resistors with current sources is a reduced requirement for resistors in the circuit; the reference voltage associated with M3 can be used elsewhere in a typical circuit.
Additionally, as will be shown, the gain of the common-source stage is substantially improved over that with actual bias resistor RD. The specific circuit of Fig. 10.1 is that for the project amplifier. The bias and gain of the amplifier are evaluated in the following.

Figure 10.1. Common-source amplifier with driver transistor M1 and currentsource load from drain of M2. In the amplifier project, an output channel sets

VG1 for a given current and another output channel will search for the VSS to set up bias VO = VDD/2. For the signal measurements, a signal voltage is superimposed on the dc VG1.

10.1. DC (Bias) Circuit
The bias circuit is critical in terms of getting the dc output voltage at a value near the project design value of VO = VDD/2 (for maximum output magnitude and linearity). The relation, from the dc circuit analysis, for obtaining this condition is based on ID1 = ID2.
This is, in terms of the transistor characteristic equations, (3.8),
Equation 10.1

Note that the source-gate voltage of M2 is referenced to M3. A certain combination of
VGS1 and VSS will satisfy Vo = VDD/2. In the project on the amplifier, a LabVIEW VI sends out a VG1 = VGS1 to set up a given ID1 = ID2 and then adjusts VSS to obtain the desired bias output voltage.
Figure 10.2 shows a SPICE plot of the current for the PMOS and NMOS transistors as a function of VDS1. The source – drain voltage for the PMOS is VSD2 = VDD – VDS1. Both transistors have a specific gate – source voltage. The solution for the output voltage for this case is about 3 V. A slight decrease in VGS1 or a slight increase in VSG2 is required to bring VDS1 to 5 V, the design result in this example. The increase in VSG2 would be implemented by making VSS more negative to increase the reference current. The steeper slope in the active region of the PMOS device is consistent with λp > λn, as in the project amplifier. Figure 10.2. Plot of driver and load transistor output characteristics on common voltage scale. Since ID1 = IDn = ID2 = IDp, VDS1 = VO is where currents intersect.
The current from the current source load needs, in this example, to be slightly increased to set VDS1 = VO, with VDD = 5V.

10.2. Signal Voltage Gain
The expression for the gain of the basic common-source amplifier, (5.4), which includes the output resistance of the driver transistor, is

In the signal circuit, as shown in Fig. 10.3, RD is replaced by 1/gds2. The new equation for this circuit is
Equation 10.2

Figure 10.3. Linear circuit of the common-source amplifier. The load is now the output resistance of the current source load, 1/gds2.

or with gm = 2ID/Veff, (4.5), and gds

ID λ, (4.13),

Equation 10.3

The result shows that the gain increases for decreasing Veffn1. This is limited by the fact that the MOSFET ceases to behave in the normal manner at some lower limit on Veffn.
Using
the gain. This is

an alternative form is obtained, which reveals the ID1 dependence of

Equation 10.4

Increasing gain is achieved with decreasing the level of bias current. The lower limit is, as noted above, associated with a lower limit on Veffn. Also, there is an approximate inverse trade-off between frequency response limitations, on the high end of the spectrum, and gain.
The gain, though, for the amplifier with current source load, will generally be several times as large as that with the resistive load. An amplifier with even higher gain can be obtained by replacing the current source load with one with source degeneration as discussed in Unit 9.2, and as discussed extensively for the case of the BJT in Unit C.

10.3. Summary of Equations
Output drain-current balance equation. Voltage-gain equation.
Voltage-gain equation in terms of λ's and Veffn1.
Voltage-gain equation in terms of λ's and ID.

10.4. Exercises and Projects
Project Mathcad
Files

Exercise10.mcd - Project10.mcd

Laboratory Project
10

Current Mirror and Common-Source Amplifier with CurrentSource Load

P10.2

Evaluation of the Current-Source Circuit

P10.3

Evaluation of the Mirror-Current Circuit

P10.4

Evaluation of the Bias Setup

P10.5

Measurement of the Amplifier Gain versus Drain Current

Unit 11. Operational Amplifiers with Resistor Negative
Feedback
In the following units we consider the operational amplifier in the basic resistive feedback amplifier configurations. We discuss gain, dc offset, and frequency response. In projects, the opamp is implemented in the noninverting amplifier mode to evaluate voltage again, opamp offset, bias stabilization, and amplifier and opamp frequency response. 11.1. Operational Amplifiers with Resistance Feedback
In this unit, the gain characteristics of the operational amplifiers with resistive feedback are discussed. These are dc amplifiers that are configured for specific gain and input and output resistance characteristics. The operational amplifier without feedback is in the open-loop mode. The dc (bias) configuration is shown in Fig. 11.1. Due to imbalances in the amplifier circuit, which are a result of variations in the parameters of the transistors and circuit components from the values used in the design, the output will probably be latched at either the plus or minus power supply.

Figure 11.1. Open-loop amplifier. Inputs, output, and power-supply pins are connected. Circuit will be bias unstable. Dc VO is likely to be latched at near VDD or VSS.

The circuit can be set into a stable, active mode with the output approximately at zero volts by providing resistive negative feedback as shown in the circuit diagram of Fig.
11.2.

Figure 11.2. Opamp resistor network, including feedback resistor for bias stabilization. Signal output voltage is Vo = avoV .

The resistor connected between the output, VO, and the inverting (minus) input effectively applies the output voltage to the opamp input and it is of such a polarity as to drive the output toward zero volts, where it tends to stay. That is, attaching the resistor completes the negative feedback loop from V to VRy. The quantitative aspects of stabilization with the feedback resistor are discussed in Unit 11.6.
This circuit becomes a dc amplifier by installing a signal at either input. These two possibilities are discussed in the following units.

11.1.1. Voltage Gain of the Noninverting Resistor Feedback Amplifier
In the circuit diagram of Fig. 11.3, an input signal voltage Vs is attached to resistor Rx.
By definition, the output terminal voltage is positive for a plus input. Hence, this is the noninverting amplifier. Here we obtain the relationship between the amplifier gain, avo =
Vo/Vs, and the open-loop gain (opamp gain), avo = Vo/V , and the circuit resistors.

Figure 11.3. Non-inverting or voltage amplifier (series-shunt). The input resistance is essentially infinite.

With a signal applied to the plus input terminal, the responding output voltage is fed back to the resistor Ry. The voltage across Ry, Vf, and Vo (signal) are related by
Equation 11.1

This is just the voltage-divider relation, which applies in this case, as negligible current flows into the input terminals of the opamp. Variable Vf is used in lieu of VRy to distinguish it from the dc value of the voltage across Ry. This use is also consistent with the fact that Vf is technically a signal feedback voltage.
The input signal voltage Vs adds up to
Equation 11.2

where (11.1) is used to eliminate Vf. (The voltage drop across Rx is essentially zero.) This leads directly to the relation for amplifier gain, which is
Equation 11.3

with (ideal noninverting gain).
Equation 11.4

. This is
AvNI is the limiting form of the noninverting amplifier gain for avo consistent with the fact that in the limit, V
0 and Vs = VRy. Thus, the output and input voltages are simply related by the voltage-divider relation. The result, (11.3), indicates that for avo>>AvNI, the voltage gain can simply be expressed in terms of the resistors and therefore is very predictable. If we make, for example, Rf = 10Ry, AvNI = 11, and (11.3) gives Av = 10.998, with avo = 40,000. The value for the opamp gain is typical for our project opamp. Note that due to the high resistance at the opamp input terminals,
Rx has no influence on the gain.
The noninverting amplifier has a very high input resistance and a low output resistance, as discussed in Unit 11.4. The amplifier technically falls into the category of a series – shunt feedback configuration or a voltage amplifier.

11.1.2. Voltage Gain of the Inverting Resistor Feedback Amplifier
To obtain the inverting amplifier, the signal is applied to the negative or inverting terminal as shown in Fig. 11.4. A positive signal results in a negative output voltage. The gain expression can be obtained with the loop equation from output to input:
Equation 11.5

Figure 11.4. Inverting or transresistance amplifier (shunt – shunt). The input resistance is equal to the signal-source resistance, Ry.

and the loop equation at the input (voltage drop across Rx is zero)
Equation 11.6

Eliminating Is between (11.5) and (11.6) gives
Equation 11.7

This expression can be manipulated to give the gain as
Equation 11.8

which is
Equation 11.9

where
Equation 11.10

AvI is the gain of the ideal inverting amplifier.
The ideal gain, as in the case of the noninverting amplifier, depends only on resistor values. The approximate form is based on the approximation V =
0, in which case the negative input terminal is at virtual ground. Thus, |vo| and Vs are proportional to Rf and Ry, respectively. The inverting-amplifier gain result includes the fact that the current into the negative terminal is zero. The circuit is a shunt – shunt feedback configuration or a transresistance amplifier.

11.2. Output Resistance of the Resistor Feedback Amplifier
The negative feedback of the amplifiers will alter the output resistance of the circuit. In the case of series – shunt feedback (noninverting amplifier) and the shunt – shunt
(inverting amplifier), the output resistance will be reduced from that of the open-loop amplifier. This can be explained with the use of the circuit of Fig. 11.5, which shows a linear-model circuit for the amplifiers of Figs. 11.3 and 11.4, with the inputs set to zero.

Figure 11.5. Linear equivalent circuit for deriving opamp output resistance. Test voltage, Vo, is applied at the opamp output. The inputs are grounded for deriving the output resistance.

For the present purposes, a voltage-dependent voltage source equivalent circuit for the opamp is chosen. The parameter ro is the output resistance of the open-loop opamp. For example, the output resistance would be about 1/gm in a CMOS opamp with a sourcefollower stage-output stage.
A test voltage, Vo, is applied at the output terminal with the input grounded. This results in an input to the opamp of magnitude V = Vo/AvNI. The voltage-dependent voltage source of the opamp is thus (avo/AvNI)Vo. The total current, Io, flowing from the test voltage is then
Equation 11.11

Therefore, the output resistance is
Equation 11.12

where T = avo/AvNI (i.e., the loop gain of the feedback amplifier). The approximate form comes from the expectation that ro >Numeric).



On the Front Panel, place a Digital Control for the resistor value.
(Controls>>Numeric.)



In the Diagram (below) place a Divide operation.
(Functions>>Numeric>>Divide.)



Wire the Diagram as in the example.

Procedure


Set your value of RG2 in the Digital Control (MΩ). To set in three digits,

change the precision. Right Click on the Control, go to Format and
Precision, and change Digits of Precision.



Run VI_02.vi with Chan0_out set at 5 V and note the value of IRG.
Default and save the Front Panel for comparison with the Mathcad evaluation file. For Default, menu Operate>>Make Current Values
Default.

P1.3. Resistor Voltage Divider with Resistor Measurement

Basic sample shown below.

Programming Exercise 1.3


Save a copy of VI_02.vi with a new name and add Digital Indicators for
VRG1 and RG1 as in VI_03.vi (basic sample below). The new VI will find and indicate the value of RG1.



In the Diagram, we will add Get Y Value.vi. This VI is found in the
Functions Palette with the sequence shown on the left.



Note that the full Palette Set is required. Your Palette may be an abbreviated form called Basic. If so, open the Palette and use the Stick
Pin to keep it open. Then Click on Options as shown below. Select the default Palette Set.



Get Y Value.vi is used to extract a given Y value in a waveform. AI
Sample Channel.vi is a special case of a waveform with only one component. In the VI of part P1.2, we connected the output directly to a
Digital Indicator, in which case, LabVIEW sorted out the component value automatically.



Place Get Y Value.vi as shown in the Diagram (cursor, Arrow). Connect the balance of the circuit as shown. The new math formulations are indicated below and in the Diagram.

LabVIEW Computations

Procedure


Run the VI_03.vi for Chan0_out set at 10 V. Note the value of RG1 and
VRG1. Default and save the Front Panel for the Mathcad evaluation file.

P1.4. Resistor Voltage Divider with a Sine-Wave Source Voltage

Procedure


The VI sends out, on Chan0_out, a sine-wave superimposed on the dc value. Add the connection, Chan1_in, directly to the output channel.
Run the VI for various values of Chan0_out. Note that the maximum allowed Chan0_out is about 6 V since the dc and ac peak must be less than 10 V. Verify that the results are consistent. For example, the peak ac values must be 1.5 of the dc values since Vs = VDD/2. Default and save the Front Panel using Chan0_out = 4V.

P1.5. Frequency Response of a Resistor-Capacitor Circuit

Components
C1 = C2 f3dBhi = 50f3dBlo
Rs

RG/50

f3dBlo = 5 Hz (approximately)

Typical C1

0.5 μF

Procedure


Configure the circuit for the low-end measurement and f3dBlo. Install C1 and do not install C2. Run VI_05.vi to obtain f3dBlo. Obtain a Log of the
Front Panel to save the results. To obtain a Log, go through menu sequence Operate>>Data Logging>>Log. To retrieve data:
Operate>>Data Logging>>Retrieve.



An example of retrieving a Log using VI_01.vi is shown here. Note that at the first Data Logging, you will be asked to name a Data Log file.

Select any name and Click Save, to install Log File in the Project folder.



Now move the capacitor C2 = C1 to the C2 location and install a large capacitor, C1new, in place of C1, which satisfies C1new >> C2 (e.g., C1new =
47 μF). Note that the source side of the capacitor (connected to Rs) is more negative than the output side (Chan0_in). Run VI_05.vi to obtain f3dBhi. Default and save the Front Panel. Note that when reopening the
VI, the Front Panel will contain the information last defaulted from this f3dBhi measurement. The first measurement is in the data Log.
Repeating, to retrieve the information from the data Log, go through menu sequence Operate>>Data Logging>>Retrieve. To then go back to the defaulted Front Panel, click OK and go through
Operate>>Reinitialize All to Default Values.



Note that if C2 = C1 are actually both in the circuit at the same time, the output in the plateau region is 1/2 as large (Exercise 1). This configuration is not implemented here. The use of C2 = C1 is only for convenience and f3dBlo >Ring and
Enum>>Menu Ring).



In the Diagram (below), place, from left to right, one Case Structure:
Functions>>Structures>>Case, and two While Loops:

Functions>>Structures>>While Loop.



On the Front Panel, using the Text Tool (Shift/Right Click for Tool Palette) in the Menu Ring, type 10 V. Right Click on the Menu Ring and execute Add
Item After. In the new listing, type 6 V. Go to the Diagram and wire the output of the Menu Ring to the "?" on the edge of the Case Structure. Note that the Items correspond to integers 0 and 1 at the terminal.



In the Diagram, place two copies of AO Update Channel.vi in the first (left)
While Loop and place AI Sample Channel.vi in the right-hand Loop. In the latter, also place Get Y Value.vi (Functions>>Waveform>>Waveform
Operations>> Get Y Value.vi). Connect the constants and Front Panel terminals as in the example.



Install constant values 10 and 6 in the 0 and 1 case states, respectively, and wire to the value terminal of the Chan0_out AO Update Channel.vi icon.



Configure the current computation function as in the example (lower-right side in Diagram) and wire to the current Digital Indicator and resistor Digital
Control. Optionally, relabel the Digital Controls and Digital Indicators according to their functions (as in AmpP2.1.vi).

Procedure


Connect the circuit using the RD selected. Install the value of RD(MΩ) in the
Digital Control. To obtain three digits of precision in the resistor Digital
Control, Right Click on the Control and go to Format and Precision... Set
Digits of Precision.



Run AmpP2.1.vi with VDD (Chan0_out) set at 10 V. Adjust VGS

(Chan1_out) for a drain voltage, VDS, of roughly 8 to 9 V. Obtain a log of the Front Panel to preserve the current (ID) and VGS information for the
Mathcad file. Reminder: Data Logging is under the Operate menu.


Now reset VDD to 6 V and re-run. Note that VDS drops by roughly 4 V, indicating that the transistor drain terminal is a current source. Note that the change in the ID indicated is only slight.



Reset VDD = 10 V. Increase VGS by an amount that makes VDS about 2 to
3 V. Note the increase in drain current. Log the Front Panel to preserve the information for the Mathcad file.

P2.2. NMOS Common-Source Amplifier with Resistor Gate Bias
Circuit

Components

Programming Exercise 2.2


Save a copy of AmpP2.1.vi (your name) and give it a new name.



As in the example (below), use three While Loops to send Chan0_out and receive on Chan0_in and Chan1_in. Note that the index "i" of a loop on the left is connected to the border of the following Loop to establish the proper order of execution of the program.



Provide Digital Indicators for VGS and VDS.

Procedure


Run AmpP2.2.vi with VDD set at 6 V to obtain VGS of about 2 V (due to RG1 2RG2). Rerun and adjust VDD to obtain VDS equal to about one-half of VDD. Note that decreasing VDD raises VDS toward VDD.
Default and save the Front Panel for the Mathcad evaluation.

P2.3. Amplifier with Signal and Gain Measurement

Programming Exercise 2.3 follows below.
(Advanced-Optional)
Procedure


Move the bottom of RG2 from ground to Chan1_out. The VI will send out a

sine-wave signal via this channel with peak Vs. Set Chan0_out (VDD) as in the circuit for P2.2 above (for VDS VDD/2).


Run AmpP2.3.vi (Project02.llb) for various values of Vs. Re-set for a Vo peak of about 1V (VDS/3). Note the gains, which are Vo/Vs and Vo/Vg.
Verify that the gain from the source is about two-thirds of the gain the gate, based on the selection (ratio) of the gate bias resistors. Default and save the
Front Panel for the Mathcad evaluation.

Programming Exercise 2.3


Make a copy of AmpP2.2.vi with a new name.



Go to the Diagram and delete all except Control and Indicator terminals.



Install a Sequence Structure in the Diagram (below). In the first Frame, install
AO Update Channel.vi. (Functions>>Data Acquisition>>Analog Output.)
Press Ctrl and drag (with Arrow Tool) an additional copy, also in Frame 0.



Connect a voltage-out (VDD, Chan0_out) value as shown in the example.
Connect a numeric 0 (value) to set Chan1_out initially to 0 V for the dc measurements. Connect channel numbers (String) and device number
(Numeric, 4 in the example).



Add a Frame After. In this Frame (1), install two copies of AI Acquire
Waveform.vi. (in menu Functions>>Data Acquisition>>Analog Input.)
These will be used for the dc measurements. A given node voltage will be sampled 100 times and the samples will be averaged for the result. Connect constants to the icons as shown in the example. These include device
(Numeric, 4, default), channel (String), number of samples (Numeric, 100), sample rate (Numeric, 10000), high limit (10 V) and low limit (0 V).



Place two copies of Get Waveform Components in Frame 1 (Palette
Functions>>Waveform>>Get Waveform Components). Then Left Click on the output (right side) of these and select "Y". Connect the inputs to the waveform outputs of AI Acquire Waveform.



Connect the outputs of Get Waveform Components to the inputs of Mean.vi functions. These are located in Functions>>Mathematics>>Probability and
Statistics or in Functions>>Analyze>>Mathematics>>Probability and
Statistics. Connect the outputs of the Mean.vi icons to the terminals of the
Digital Indicators of VDS (Chan0_in) and VGS (Chan1_in).



Add a Frame After (2). In this Frame we place a general-purpose function generator and oscilloscope function. This is FG1Chan.vi and is in
Functions>>User Libraries>>FunctGen. A Digital Control and a Digital
Indicator are required for this Frame. Install Digital Control, Vs, and Digital

Indicator, Vo.



Connect to FG1Chan.vi, the various terminals, constants, and strings. The connections include Frequency (Numeric, 50), Vacin (Vo), Chan_out (String,
1), Sinewave - SqWave (False), Graph Out (leave disconnected for now),
Chan_in (String, 0), Vs (Digital Control), and VDCout (Numeric, 0).



Now add another Frame after (3). In this Frame, install the same function,
FG1Chan.vi. This can be copied and pasted from Frame 2. Add, in the Front
Panel, an additional Digital Indicator, Vg. Make the connections the same as in Frame 2 except Chan_in (String, 1).



In Frame 2, configure, using a divide function, Vo/Vs, as shown in the example. Add a Digital Indicator in the Front Panel with the label Vo/Vs and connect the output from the divide function to the terminal of this Digital
Indicator.



Click on the edge of Frame 2 and install Add Sequence Local and, to this,
Connect Vacin (Vo). Move to Frame 3, install a Divide function, and configure Vo/Vg as in the example. Note that Vo comes from the Add
Sequence Local from Frame 2. In the Front Panel, add an additional Digital
Indicator to read Vo/Vg.



Now add the graph in the Front Panel. (A detailed description of using a graph is given in Section A.1.5.) The graph for this case is a Waveform
Graph. Get this in the Front Panel under Controls>>Graph>>Waveform
Graph. Use the Coloring Tool to adjust the color of the graph background by
Right Clicking on the graph with the Coloring Tool. Right Click on the sample trace in the Plot Legend to adjust the color of the trace. Using the
Operating Tool, Right Click on the X Scale or Y Scale>>Formatting to set the
Grid Options.



Configure the Diagram for connecting to the graph. Outside the Sequence
Structure and on the right, install a Build Array function.
(Functions>>Array>>Build Array.) Connect the Plot output of FG1Chan.vi

in the two Frames, 2 and 3, to the two inputs of Build Array. Connect the output of Frame 2 on the top input.

Laboratory Project 3. Characterization of the PMOS
Transistor for Circuit Simulation
P3.1 SPICE Parameters and Pin Diagram
P3.2 SPICE Equations
P3.3 PMOS Transistor
P3.4 Low-Voltage Linear Region of the Output Characteristic
P3.5 PMOS Parameters from the Transfer Characteristic
P3.6 PMOS Lambda from the Transfer Characteristic
P3.7 PMOS Output Characteristic
P3.8 PMOS Lambda
Exercises and Analysis Exercise03.mcd - Project03.mcd

P3.1. SPICE Parameters and Pin Diagram
SPICE PARAMETERS
SPICE Name

Math Symbol

Description

VTO

Vtno, Vtpo

Zero VSB threshold voltage.

KP

Transconductance parameter.

GAMMA

γn, γp

Threshold voltage parameter.

LAMBDA

λn, λp

Active-region slope parameter.

CD4007 Pin Diagram

SPICE PARAMETERS
SPICE Name

Math Symbol

Description

P3.2. SPICE Equations
SPICE Equation (PMOS)

NMOS
Eq.

Description

3.2

Output characteristic low-voltage conductance. 3.10

Output characteristic for full linear range (0
0.5 V. The maximum ID is set for 0.1 V. Run the VI to obtain parameters as indicated in the Front Panel. Default and save the Front Panel to save information for the Mathcad analysis.

P3.5. PMOS Parameters from the Transfer Characteristic

Components

LabVIEW Computations

Procedure


Run PMOSparsub.vi with VSD = 3 V and VSD = 9 V. VDD
(Chan0_out) starts at 2 V such that the minimum current is IDmin = (2 V
– VSGmin)/RS. ID stops automatically at ID = 500 μA or Chan0_out =
10 V. Verify that the VI functions properly. PMOSparsub.vi will run as a subVI of the next VI.

P3.6. PMOS Lambda from the Transfer Characteristic

Components

LabVIEW Computations

Procedure


Run PMOSparam.vi to run subVI PMOSparsub.vi at VSD = 3 V and
VSD = 9 V to resolve Lambda and final values of kp and Vtpo. Default and save the Front Panel to save the parameter values for the Mathcad results analysis file.

P3.7. PMOS Output Characteristic

Components

LabVIEW Computations
Linear Region

Active Region

Procedure


Install PMOS parameters from P3.6 into the Front Panel of
PMOSoutput.vi. A given VSD sweep will halt at Chan0_out = 10 V.
Set VSGstart(V) as necessary to obtain ID 100 μA for VSD in the active region. Verify that the measured data and SPICE calculation agree reasonably well. Write in you file path and save a data file for Mathcad.
The file will contain the data points for the highest current output characteristic. Default Front Panel and save. These data will be used in the Mathcad analysis file.



With the data defaulted and saved in the graph of the VI, a data file can be obtained at a later time. From the Diagram of PMOSoutput.vi, click on XYtoDataFile.vi, copy the data from PMOSoutput.vi, and paste it

into the Control Graph of XYtoDataFile.vi. Name the path and data file and run the VI. XYtoDataFile.vi is located in the User.lib in the
LabVIEW folder. Therefore, it can also be opened from the Diagram of a
VI under Functions>>User Libraries>>Dat_File.

P3.8. PMOS Lambda
LabVIEW Computations
Straight-line curve fit from active region data:
ID = Slope · VSD + IDo λp = Slope/IDo kp = IDo/Veffp2
Procedure


Lambda.vi is configured for Enable Data Base Access to read the data from PMOSoutput.vi. Lambda.vi can read all of the Front Panel information in PMOSoutput.vi when a log of the Front Panel has been obtained. •

From the Diagram of Lambda.vi, open PMOSoutput.vi. Obtain a data log of the Front Panel of the PMOSoutput.vi (under Operate Menu).



Run Lambda.vi to read the graph of measured data (from
PMOSoutput.vi) and to plot the measured data from the active region.
The VI obtains Kp and λp from these data, for each of the voltage sweeps. Note that Lambda varies. Compare the average Lambda value with that from PMOSparam.vi.



Click on Call PlotID_VSD.vi Green to bring up a plot of the activeregion equation plot for –1/λp < VSD < VSDmax, compared with the measured data. Lambda.vi will be used in the Mathcad analysis file.

Laboratory Project 4. Characterization of the NMOS
Transistor for Circuit Simulation
P4.1 SPICE Parameters and Chip Diagram
P4.2 NMOS Transistor
P4.3 SPICE Equations
P4.4 NMOS Parameters from the Transfer Characteristic
P4.5 NMOS Lambda from the Transfer Characteristic
P4.6 NMOS Gamma SubVI
P4.7 NMOS Gamma
P4.8 NMOS Circuit with Body Effect
Exercises and Analysis Exercise04.mcd - Project04.mcd

P4.1. SPICE Parameters and Chip Diagram
SPICE PARAMETERS

SPICE Name

Math Symbol

Description

VTO

Vtno, Vtpo

Zero VSB threshold voltage.
Transconductance parameter.

KP
GAMMA

γn, γp

Threshold voltage parameter.

LAMBDA

λn, λp

Active-region slope parameter.

CD4007 Pin Diagram

P4.2. NMOS Transistor
Use CD4007 pins 3 (gate), 4 (source) and 5 (drain). Connect pin 4 (source) to pin 7
(body). Connect PMOS body (pin 14) to the most positive node in the NMOS measurements, Chan0_out or ground, depending on the circuit. In the γn measurement
(NMOSgamma.vi) and the transfer characteristic measurement (NMOS_Cir.vi), pin 14 is connected to ground. Note that the NMOS of pins 6, 7, and 8 has internally connected body and source. This transistor is used in a following project.

P4.3. SPICE Equations
SPICE Equation

Description
3.8

Active region transfer characteristic and output characteristic (VDS > Veffn,
VSB = 0).

SPICE Equation

Description
3.12 Active-region equation solved for
VSG.

3.14 Threshold voltage dependence on
VSB.
X variable for Vtn versus X plot in γn determination. P4.4. NMOS Parameters from the Transfer Characteristic

LabVIEW Computations

Components

Procedure


Set RS value. Run NMOSparsub.vi and adjust VSSinit for a minimum
ID 50 μA. Test run NMOSparsub.vi with VDS = 3 V and 10 V.
Execution halts at ID 500 μA. The VI runs as a subVI in the next part.
Default and save. Saved VSSinit is used in the Top VI in the next part.

P4.5. NMOS Lambda from the Transfer Characteristic

Components

LabVIEW Computations

Procedure


Set RS. Run NMOSparam.vi to obtain a set of NMOS parameters. The
VI runs NMOSparsub.vi automatically with VDS = 3 V and VDS = 10
V. The sweep stops at ID 500μA or |Chan0_out| = 10 V. Default and save the VI.

P4.6. NMOS Gamma SubVI

Components

Note: VGS will be larger with the body effect.

Procedure


Note that PMOS body pin 14 and the NMOS drain terminal are at ground. Set RS and VSSinit from NMOSparsub.vi. Run
NMOSgamsub.vi with VSB = 0 V and 3 V to verity that circuit is functioning properly. Note the change in the VGS range for the larger
VSB. VSSinit is adjusted automatically for larger values of VSB, to obtain, approximately, a starting ID of about 50 μA. Default and save the Front Panel to save VSSinit.

P4.7. NMOS Gamma

Components

LabVIEW Computations

Procedure


Set RS. With NMOSgamsub.vi open, run NMOSgamma.vi to obtain
Gamma. Adjust 2φF to try to match Vtno (intercept, curve fit) with Vtno
(VSB = 0, transfer characteristic, graph on right). Save the results.

P4.8. NMOS Circuit with Body Effect
Components
Use RS from NMOSgamma.vi.

Procedure


Set RS. Install SPICE parameters from NMOSparam.vi and
NMOSgamma.vi. Run NMOS_Cir.vi to obtain ID versus VGS with a sweep of VSS. The iteration solution obtained in SPICEgamma.vi
(Diagram below) is compared in the graph of NMOS_Cir.vi. Adjust
VSSinit to obtain IDmin of about 50μA. Re-adjust Gamma for best fit.
Then save a data file with your data file name. The data file must be in the folder with the Mathcad file. The file name must have a *.prn extension.



A file can be obtained from the graph of the defaulted and saved VI using
XY1toDataFile.vi. The VI XY1toDataFile.vi is located in \\LabVIEW
6\User.lib\Dat_Files\Dat.llb.



Note that XY1toDataFile.vi is different from XYtoDataFile2.vi, as used to obtain a data file in the Diagram of NMOS_Cir.vi. The Control Graph

of XYtoDataFile2.vi accepts single plots while XY1toDataFile.vi is for graphs with two Y functions (with only one Y function in the data file).
For convenience, a copy of XY1toDataFile.vi, GetDataFile.vi, is included in the Project04.llb. For clarification, XY1Y2toDataFile.vi accepts graph data with two Y functions and includes both in the data file.

Laboratory Project 5. PMOS Common-Source
Amplifier
P5.1 SPICE Equations and Pin Diagram
P5.2 PMOS Common-Source Amplifier DC Setup
P5.3 Amplifier Gain at One Bias Current
P5.4 Amplifier Gain versus Bias Current
Exercises and Analysis Exercise05.mcd - Project05.mcd

P5.1. SPICE Equations and Pin Diagram
CD4007 Pin Diagram

SPICE Equation

Description
3.8
(NMOS)

DC drain current voltage relation
(PMOS).

CD4007 Pin Diagram

SPICE Equation

Description
5.6

Gain versus ID.

5.7

Gain versus ID, Veffp.

P5.2. PMOS Common-Source Amplifier DC Setup

LabVIEW Computations

Components

Procedure


Install RD value. Adjust VSG in SetVSD.vi and run the VI to find the value for IDMAX = 500 μA ± 50 μA. VSS is ramped up from 10 V
(default value) to find the value for VD = –4 V. Note that if RD is too large, VD will be > –4 V initially (for VSS = –10 V) at IDmax. Default and save the Front Panel.

P5.3. Amplifier Gain at One Bias Current

LabVIEW Computations

Components
Same as SetVSD.vi
SubVI's
SetVSD.vi (Set Bias)

FG1Chan.vi (Function Generator)
SR.vi (Send-Receive Function)
Oscilloscope.vi (Chan1_in Read Waveform)

Procedure


Sub VI FG1Chan.vi sends out the bias VSG and, in series, a sine-wave signal equal to VSG/20. Set VSGinit as determined with SetVSD.vi as the
VSG required to obtain ID 500 μA. This is the initial VSG in the sweep of the next part. Run the VI to obtain the gain for this bias current. Obtain a data log of the Front Panel. Default and save. Re-run with a new VSGnew = VSG – 0.5 V to obtain the gain at a lower bias current. Obtain a data log.

P5.4. Amplifier Gain versus Bias Current

LabVIEW Computations

Components
Same as SetVSD.vi
Sub VI's
GainSub.vi
SetVSD.vi (Set Bias)
FGsine.vi (Function Generator)
SR.vi (Send-Receive Function)
Oscilloscope.vi (Chan1_in Read Waveform)

Procedure



Run Gain.vi to run GainSub.vi over a range of currents. Set
VSGinit(V) to the value obtained above for ID 500 μA (defaulted in
SetVSD.vi). The VI automatically halts (decreasing) at ID 50 μA.
Default and save the Front Panel. Now obtain a data file as follows.



Open GraphToDataFile.vi (copy of XYtoDataFile.vi) in Project05.llb.
Copy the data from the graph ID versus VSG of Gain.vi. (Right Click on the graph, then Data Operations>>Copy Data.) Then paste the data into the Control Graph of GraphToDataFile.vi. (Right Click on the graph and then Data Operations>>Paste Data.) Type the data file path and name the data file. Run the VI to obtain a data file to be read by the
Mathcad evaluation file. Repeat for the gain plot, av versus ID. Recall:
The data files must be in the folder with the Mathcad file. The file name must have a *.prn extension.

Laboratory Project 6. PMOS Common-Source
Amplifier Stage with Current-Source Biasing
P6.1 PMOS Schematic and Pin Diagram
P6.2 SPICE PMOS and Circuit Equations
P6.3 PMOS Current-Source Amplifier DC Setup
P6.4 Amplifier Gain
P6.5 Amplifier Frequency Response
Exercises and Analysis Exercise06.mcd - Project06.mcd

P6.1. PMOS Schematic and Pin Diagram
CD4007 Pin Diagram

P6.2. SPICE PMOS and Circuit Equations
SPICE Equation

Description
3.8
DC drain current –
(NMOS) voltage relation
(PMOS).
5.15

Midfrequency gain versus ID.

5.6

Midfrequency gain versus ID with bypass capacitor Cs.

6.1

Gate signal voltage,
Vg, frequencydependent relation to signal source, Vs.

6.4

Gain frequency response with Cs only
(Cg infinite).

6.9

Approximate f3dB with Cg infinite.

P6.3. PMOS Current-Source Amplifier DC Setup

Components

VSG versus ID from Lab Projects 4,5.
LabVIEW Computations

Procedure


Install your value of RS in the Front Panel. Verify that VDD = 10V. Run
DC.vi to verify your selection of RS RD. Goal is ID 300 μA. Verify

that VG is about VDD/2. Default and save the Front Panel. Note that
VSD is about 2VSG.

P6.4. Amplifier Gain

LabVIEW Computations

Use Project06.mcd for calculations.
SubVI's
FG1Chan.vi
SpecAnaly.vi
LabVIEW Computation

Procedure


The SubVI of Gain.vi, FG1Chan.vi, sends out a signal with sine-wave peak Vs (Chan1_out). The first measurement is with only capacitor Cg installed. Be sure to conform to the capacitor polarity requirement. Set the Signal Frequency to 1000 Hz. Set your value of RS and check VDD
= 10 V. Run Gain.vi to measure the gain. The gain should be less than 1 without the source bypass capacitor. A signal of Vs 0.5 V should thus suffice for good linearity and measurement precision.



Now install the capacitor Cs. Note that the source is at a positive voltage.
Run the VI while setting Vs at various values. Adjust Vs until the

THD% (total harmonic distortion, %) is reduced to below about 5%.


Continue to lower Vs and run Gain.vi. Verify that the measured gain, av, is invariant for smaller values of Vs except as eventually limited by
DAQ resolution and noise. Find the largest Vs (up to 5% THD), which is consistent with a constant gain measurement with increasing Vs.



Run the VI again with a lower frequency (e.g., 800 Hz) to verify that the gain is not frequency dependent in this frequency range. Now default and save the Front Panel.

P6.5. Amplifier Frequency Response

Procedure


The frequency of the input source voltage is swept from 1 to 1000 Hz to
1000 Hz. Set Vs in FreqResp.vi as determined above for a valid voltage gain measurement. Open FG1Chan.vi to observe the waveform at the output. •

Set your value of RS. Run FreqResp.vi without Cs. Recall that the gain will be less than 1. The frequency response is dictated by Cg only. Verify that f3dB is about equal to or less than 1 Hz. Note that f3dB Veffn. This is the requirement to be in the active region. In the example, the design drain current is IDmax = 300 μA.



Verify that as VDD is reduced, ID decreases and VDS increases. Check
VDD = 4 V, the minimum in the sweep for parameter measurement of the next part. Verify that at the minimum VDD, VDS > ID·RD Obtain a log for Chan0_out = 10V.



Reduce VDD from the maximum VDD = 10 V and determine,

approximately, the value between 4V < VDD < 10V that corresponds to
VDS IDRD. This is the operating point (bias) condition for the amplifier gain measurement. This will be found automatically in the gain measurement VI.

P7.3. Amplifier Gain at Optimum Bias for Linear Output

Components*

Note that gm is in μA/V.
*

Run the first part of Procedure with GainNMOS.vi, below, without the capacitor, to obtain Veffn and bias ID, for computing gm.

LabVIEW Computations
Parameters: Vtno, kn

Procedure (Obtain Parameters and Bias Variables)


Open GainNMOS.vi. Install your RS value. Without the capacitor installed, set the Mode Switch to Param (red, switch in logic state 0).
Run the VI for a VDD sweep to get the parameters. (Note: The sweep rate is configured to be slow in case the capacitor is in place during the sweep.) The VDD sweep is from 4 V to 10 V. Obtain a log of the results.

Procedure (Gain Measurement)


In the Param mode, the VI finds and indicates VDDbias corresponding to the optimum VDS = (VDD – VRs + Veffn)/2. This permits maximum signal swing without distortion. Set the indicated value of VDDbias into the Set VDD Digital Control. Run the VI with the Mode Switch set to
Gain (green, switch position logic 1) without the capacitor. Obtain a log of the Front Panel. Default and save the Front Panel.



At the end of the parameter sweep, Veffn is indicated for VDDbias. The value is retained in the Digital Indicator in the gain measurement. The value of ID indicated in the gain measurement is the amplifier gain bias value. Use Veffn along with bias ID, to compute gm and thus Cs. Use
Project07.mcd for the calculation.



Install the capacitor. Make certain that the polarity of the capacitor is correct. Check that the Mode Switch is set to Gain (switch position logic
1). Check that the value of VDDbias matches the value in Set VDD
Digital Control. The VI will measure the gain at this one VDD setting
(optimum for distortion-free output). The signal frequency is initially
500 Hz.



Run the VI and vary the value of Vs to determine that the gain result,
Vd/Vg, is not affected by changes, that is, by distortion. Default and save the Front Panel. Obtain a log of the results. Also, run with slight variations in Freq (e.g., 300 Hz). Note that the parameter values are preserved when running the gain mode. Parameter, bias variable, and gain data are required for the project Mathcad file.

P7.4. Optimum Bias Stability Test


As will be explored in a project Mathcad file, the basis stability computation is performed here with LabVIEW. Recall (Section 5.5) that this takes into consideration a possible range of Vtno and kn values. Here, an analysis is made regarding the extent to which your design is optimum in terms of bias stability. Note that this is separate from the

maximum signal condition that has been included in the design.



Open CalVDSoptimum.vi. In the Digital Controls, set you values for
VDD, kn, Vtno, and ID. ID is the nominal value of the design for the nominal values of the parameters. Your value of ID, along with your parameter values, will be assumed to be, for this evaluation, the nominal values. The computation holds the bias current constant at the design value (as entered into the Front Panel). As VG is increased (X axis), the added increment of VG is the added drop across the new RS, for a given new VG. Run the VI.



Verify that the value of VGS in the top Digital Indicator matches reasonably well your measured value (Front Panel of GainNMOS.vi).
This SPICE computation uses your measured parameter values and ID.
The values should be consistent.



The top graph is its VDSlimits versus VG. The center (dashed) curve is for your parameters. The downward slope reflects the increasing drop across VG. The top and bottom plots are for the two extremes of VDS that occur for the worst case of the combination of the limits of kn and
Vtno. The computation is for Vtno± = Vtno ±100 mV and
. The same optimum signal level condition as used in your design is maintained throughout.



The lower graph contains plots of the output signal limiting values. The best combination of bias stability and signal level is at the peak of these curves. •

Step through the RS Array Digital Indicator to locate your RS and the associated index. Then determine the corresponding VG and RD (same index). The value of RD should match your design value. The value of
VG should match the value from the Front Panel of GainNMOS.vi.



Locate your value of VG on the X-axis of the two graphs. If it falls in the range of values surrounding the peaks, the circuit is optimized both in terms of signal limits and bias stability. Note that bias stability was not taken into consideration in the design. In the design, though, often a given criterion serves as the basis and the design may then be evaluated for other criteria.

P7.5. Amplifier Frequency Response

Procedure


In FreqRespNMOS.vi, the frequency of the with source voltage (sinewave Chan1_out) is swept from 1 to 1000 Hz. Chan2_in should be disconnected to reduce the stray capacitance at the gate. In the Front
Panel of the VI, set VDDbias and Vs at the values determined in the gain measurement with GainNMOS.vi.



Along with FreqRespNMOS.vi, open FG1Chan.vi to observe the output waveform. Verify that Cs is installed and run the VI to obtain a value for f3dB.



Open, from the Diagram of FreqRespNMOS.vi, Frame 2,
XYtoDataFile2.vi. Run FreqRespNMOS.vi again, with the data mode switch set to Green (logic stage 1), to obtain a data file of the frequencyresponse plot in XYtoDataFile2.vi. (Note that with the data VI open, the data are transferred to the VI and can then be saved in the VI.) The data file is used in the Mathcad project file. Default and save the Front Panels of both XYtoDataFile2.vi and FreqRespNMOS.vi. Note the maximum index for the Mathcad file. The f3dB result will differ from the design, as the design was based on the simple form. This will be explored in the
Mathcad file.



A data file can be obtained later from the saved data in the graph of
FreqRespNMOS.vi, with XYtoDataFile2.vi. As noted above, the data file VI can be obtained from the Diagram of FreqRespNMOS.vi. The data file VI is located in Dat.llb in the User.lib folder (Program
Files>>National Instruments>>LabVIEW 6). The VI can also be accessed from the menu sequence in FreqRespNMOS.vi,
Browse>>Show VI Hierarchy, and open the data file VI from the
Hierarchy Window.
Return to Project07.mcd.

Laboratory Project 8. NMOS Source-Follower Stage
P8.1 SPICE Equations and Pin Diagram
P8.2 Source-Follower DC Evaluation
P8.3 Source-Follower Voltage Transfer Relation
P8.4 Source-Follower Voltage Transfer Relation with Body Effect
Exercises and Analysis Exercise08.mcd - Project08.mcd

P8.1. SPICE Equations and Pin Diagram
SPICE Equation

Description
7.1

Threshold voltage for VB = VSS.

7.7

Source-follower voltage-transfer relation with
Vsb = 0.

7.12 Source-follower voltage transfer relation with body effect.
4.11 Body-effect transconductance.
CD4007

Do not connect pin 14.

P8.2. Source-Follower DC Evaluation

Pin 14 must not be connected. Chan0_out will be plus and minus and the drain is at ground.
Components
For Gain.vi

Note that with RS is selected for the condition of maximum body-effect (VGSmax
5 V), IDmax > 500 μA for the case without body effect. The current sweep VI's halt at ID = 500 μA.
Procedure


In the Front Panel of DCcheck.vi, set the value of RS in the Digital
Control. With VSS (magnitude) set at 10 V, run the VI to verify the dc design. Note that | VS| is equal to the VGS magnitude. Verify that ID >
500 μA for this case of no body effect.

P8.3. Source-Follower Voltage Transfer Relation

Pin 14 must not be connected to ground. Chan0_out will be greater than 0 for the positive signal.
LabVIEW Computation

Procedure


GainSF.vi measures the gain (transfer relation) of the circuit over a

range of drain current. Parameters Vtno and knprime are obtained from the ID sweep. Vtno is used in the voltage transfer-relation calculation as plotted along with the measured data.



Open GainSF.vi and install your value of RS. Open FG1Chan.vi to observe the waveform at the output. Run the VI and verify that the curves match reasonably well as in the example. Adjust the magnitude of
VSS to obtain a minimum ID of about 50 μA



Adjust the value of Vs while rerunning the VI. Use the largest Vs without distortion. Large-signal distortion is manifested by a poor curve fit, particularly at the low end of the current range.



Default and save the Front Panel. The value obtained for knprime must be available for the next VI. It is used in the calculation of
. The alternative form, gm = 2ID/Veffn, is used in the calculations for this VI.



Obtain a data file of the plot using XY1ToDataFile.vi.

P8.4. Source-Follower Voltage Transfer Relation with Body Effect

Pin 14 must not be connected to ground. Chan0_out will be greater than 0 for the positive signal.
LabVIEW Computation

Procedure


Move the body pin connection as in Circuit P8.2. In GainBE.vi, install a first-guess value for γn(Project 4). Install the value of knprime, obtained from the Front Panel of GainSF.vi. Run the VI and readjust γn for the best fit. Adjust |VSS| init for a minimum ID of about 50 μA. Note the reduced value of the voltage transfer relation (gain).



Open Compare.vi from Project08.llb. Paste the results from the graphs of the plots for with and without body effect into the control graphs.
Run the VI to compare the results.



Use XY1ToDataFile.vi to obtain a data file of the plot in GainBE.vi.

Laboratory Project 9. MOSFET Differential Amplifier
Stage
P9.1 SPICE Equations and Pin Diagram

P9.2 DC Evaluation of the Single-Power-Supply Differential Amplifier
P9.3 Determination of the PMOS Parameters
P9.4 Amplifier Gain Measurement
P9.5 Transistor Parameters and DC Imbalance
P9.6 Common-Mode Gain Measurement
Exercises and Analysis Exercise09.mcd - Project09.mcd

P9.1. SPICE Equations and Pin Diagram
SPICE Equation

Description
8.34
8.40

Noninverting gain.

8.38
CD4007

Inverting gain.

Signal resistance at source node.

PMOS 1

PMOS 2

P9.2. DC Evaluation of the Single-Power-Supply Differential Amplifier

Components
RD1 = RD2 = RD
Rs = RD/2
VD

VDD/2 – VSG

For Chan0_out = 10 V:
100 μA 10 V for the last measured current, the last (invalid) data point set will be eliminated from the Mathcad data file.



Obtain a data file of the graph. Set Get File Green (logic 1) to green and write the file path and file name. Run the VI to obtain the data file. The data file is used in ProjectB2.mcd.



For obtaining a data set at a later time, such as for simulation only, open
Beta_IC.vi; retrieve the data log from the Front Panel. Then go to the
Diagram of Beta_IC.vi and open XYtoDataFile2.vi (or use
Browse>>Show VI Hierarchy). Copy and paste data and run the data file VI to obtain the file.



Open BF_NE_ISE.vi (below). Install your plot data and value of IS from Beta_IC.vi into the Control Graph and Digital Indicator, respectively. Run the VI to obtain IS, NE, and ISE. The VI performs a curve fit using (B.38). Three data-point sets used by the VI are nearest to
0.01, 0.1 and 1 mA.



The VI, CompareBetas.vi (below), is for comparing the results from the two measurements from PB.3 and PB.4. Open the VI and paste data from Beta.vi and Beta_IC.vi in the two Control Graphs. Run the VI to compare the plots. The results are expected to be very similar. This is experimental proof of the fact that IB is independent of VBC, unlike the collector current. Note that VBC = 0 V in the measurement with
Beta_IC.vi, but that VCB = IBRB in the base current measurement of
Diode_IV.vi. The latter is as high as about 9 V.

PB.5. BJT Output Characteristic Measurement

Components
Same circuit as in PB.4
LabVIEW Computations
SPICE IC versus VCE. This is performed with subVI SPICE.vi.
Straight-line curve fit from active-region data:

IC(VCE = 0) (active-region extrapolation)

ICo

VAF = Slope/ICo
Procedure


Open subVI, IC_VCEsub.vi. This VI will send out a value of VBB and sweeps VCC to sweep VCE. The maximum VCE is set for 4 V. Set the value of the resistors. Run and re-run while setting VBB for an activeregion collector current of about 0.5 mA. Note that at this collector current, a maximum VCE of 4 V should be attainable as the circuit was designed (PB.3, PB.4) for ICmax 1 mA for VRc 9V. Default and save. •

Now open VI, IC_VCE.vi. Set the value of the resistors. Set VBB from the subVI, IC_VCEsub.vi. Set VCEmax at 1 V. Run the VI and adjust
BR for a best fit. Then re-run the VI with VCEmax set at 4 V to obtain a good value for VAF. VAF is computed from data points in the range 1 <
VCE 1 mA and and that VCE is 50 to 300 mV (in saturation). •

SetVCE2.vi calculates the VCE operating point (bias voltage) as (VCC –
VREp)/ 2 for any VCC (optimum signal swing magnitude). When the Run
Mode is set to Set VCE, the execution of the VI halts when this level of
VCE is reached.



Set the Run Mode switch to Set VCE. Run the VI. Verify that the execution halts when VCE is about equal to VCE(V)Op.Pt. Note that in the example, IC = 1.14 mA for VCC = 10 V and VBB = 9.02 V. Verify that the final VCE is close to VCE(V)Op.Pt. Default the Front Panel to save the values of RBn and REp.



SetIC.vi runs SetVCE2.vi as a subVI. It ramps VCC downward to find the VCC corresponding to the design IC = 1 mA. Open SetIC.vi and have SetVCE2.vi open as well. SetIC.vi will be a subVI in the gain measurement VI. Run the VI to verify that the VI can determine the
VCC corresponding to IC = 1 mA. In the example, VCC has been ramped down to 9.0 V and VBB is now down to 8.1 V. The routine will occur automatically in the execution of the gain measurement VI.

PC.9. Measurement of the Amplifier Gain

Component Computation

Procedure


AmpGain.vi sweeps the signal frequency over the range finit…...

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